Mike Pall
d0759e41a1
Merge branch 'master' into v2.1
2017-02-20 02:39:57 +01:00
Mike Pall
ee33a1f9b3
MIPS: Fix emitted code for U32 to float conversion.
2017-02-20 02:35:00 +01:00
Mike Pall
71ff7ef8a7
Merge branch 'master' into v2.1
2017-01-17 12:41:05 +01:00
Mike Pall
b93a1dd0c8
Bump copyright date to 2017.
2017-01-17 12:35:03 +01:00
Mike Pall
e577db52c5
Increase range of GG_State loads via IR_FLOAD with REF_NIL.
...
Require 32 bit alignment and store offset/4 instead.
Otherwise this can overflow the 10 bit limit for the FOLD op2 key.
2016-11-19 19:53:46 +01:00
Mike Pall
d9986fbadb
MIPS64, part 1: Add MIPS64 support to interpreter.
...
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
Sponsored by Cisco Systems, Inc.
2016-05-28 05:10:55 +02:00
Mike Pall
786dbb2ebd
Add IR_FLOAD with REF_NIL for field loads from GG_State.
...
Contributed by Peter Cawley.
2016-05-21 01:00:49 +02:00
Mike Pall
cfa188f134
Move common 32/64 bit in-memory FP constants to jit_State.
...
Prerequisite for immovable IR.
Contributed by Peter Cawley.
2016-05-21 00:02:45 +02:00
Mike Pall
475a6ae33f
Merge branch 'master' into v2.1
2016-05-20 20:26:39 +02:00
Mike Pall
37e1e70313
Add guard for obscure aliasing between open upvalues and SSA slots.
...
Thanks to Peter Cawley.
2016-05-20 20:24:06 +02:00
Mike Pall
64c6da6b21
MIPS soft-float: Fix code generation for HREF.
2016-03-10 17:08:55 +01:00
Mike Pall
f4231949b5
Merge branch 'master' into v2.1
2016-03-03 12:11:37 +01:00
Mike Pall
db1b399af1
Bump copyright date to 2016.
2016-03-03 12:02:22 +01:00
Mike Pall
a443889677
Don't allocate unused 2nd result register in JIT compiler backend.
2016-02-10 18:51:02 +01:00
Mike Pall
f547a1425e
MIPS: Add soft-float support to JIT compiler backend.
2016-02-10 18:49:22 +01:00
Mike Pall
0a5045c34e
Merge branch 'master' into v2.1
2015-01-06 00:12:45 +01:00
Mike Pall
86913b9bbf
Bump copyright date to 2015.
2015-01-05 23:59:31 +01:00
Mike Pall
054e6abe37
Add LJ_FR2 mode: Two-slot frame info.
2015-01-03 15:04:38 +01:00
Mike Pall
2863b10956
Merge branch 'master' into v2.1
2014-02-20 15:09:02 +01:00
Mike Pall
2bc63bb6af
Prevent BASE register coalescing if parent uses IR_RETF.
2014-02-19 17:09:22 +01:00
Mike Pall
a9d4543601
Merge branch 'master' into v2.1
2014-01-16 23:18:34 +01:00
Mike Pall
ef59e54820
Bump copyright date to 2014.
2014-01-16 23:10:16 +01:00
Mike Pall
d1194a82eb
Low-overhead profiler, part 4: JIT compiler support.
2013-09-08 02:53:23 +02:00
Mike Pall
517500ba48
Save currently executing lua_State in g->cur_L.
...
This is only a good approximation due to deficiencies in the design of
the Lua/C API. It indicates _some_ valid state that is/was executing.
Also reorder L->cframe stores to achieve a synchronously consistent state.
2013-08-30 23:38:17 +02:00
Mike Pall
f1f7e40318
FFI: Compile VLA/VLS and large cdata allocs with default initialization.
2013-05-24 00:49:02 +02:00
Mike Pall
647cc4613f
Merge branch 'master' into v2.1
2013-05-16 20:07:53 +02:00
Mike Pall
0f79d4741f
Handle calls with max. args in backends even after SPLIT.
2013-05-16 19:59:38 +02:00
Mike Pall
acda75ad2c
Refactor CCallInfo representation for split arguments.
2013-05-13 19:49:46 +02:00
Mike Pall
a2c78810ca
Combine IR instruction dispatch for all assembler backends.
2013-04-22 22:32:41 +02:00
Mike Pall
2cd4ce6141
Use same HREF+EQ/NE optimization in all assembler backends.
2013-04-22 20:47:39 +02:00
Mike Pall
988e183965
Reorganize generic operations common to all assembler backends.
2013-04-22 17:34:36 +02:00
Mike Pall
5f1781a127
Compile string concatenations (BC_CAT).
2013-04-21 01:01:33 +02:00
Mike Pall
ac14d88030
Merge branch 'master' into v2.1
2013-04-04 18:20:58 +02:00
Mike Pall
389822d606
Fix spurious red zone overflows in machine code generation.
2013-04-04 17:19:31 +02:00
Mike Pall
b65196b7fd
Merge branch 'master' into v2.1
2013-02-28 17:53:45 +01:00
Mike Pall
78c97bc5a1
MIPS: Fix cache flush/sync for JIT-compiled code jump area.
2013-02-28 17:52:31 +01:00
Mike Pall
b359ce804b
Remove obsolete non-truncating number to integer conversions.
2013-02-23 01:19:00 +01:00
Mike Pall
4a44c4ff69
Bump copyright date to 2013.
2013-02-11 12:54:48 +01:00
Mike Pall
bbe35adfcd
MIPS: Compile math.sqrt() to sqrt.d instruction.
2012-10-15 21:28:10 +02:00
Mike Pall
1447ee6520
ARM, MIPS: Fix workaround for argument GPRs vs. FPR remat.
2012-10-15 15:47:15 +02:00
Mike Pall
30f458fb4d
ARM, PPC, MIPS: Improve XLOAD operand fusion and register hinting.
2012-08-27 20:25:54 +02:00
Mike Pall
4c882fe714
Replace strtod() with builtin string to number conversion.
2012-08-25 23:02:29 +02:00
Mike Pall
1fef2df3e8
MIPS: Don't use argument GPRs to rematerialize FPR arguments.
2012-08-19 18:44:29 +02:00
Mike Pall
2ac083cb5a
MIPS: Fix calls to floor/ceil/trunc.
2012-08-19 18:41:34 +02:00
Mike Pall
4da7ffc34b
Remove unneeded snapshot preps for sunk stores.
2012-07-03 23:19:45 +02:00
Mike Pall
17d3fc47f3
Avoid pesky compiler warnings about C++ keywords (eh?).
2012-07-03 13:19:32 +02:00
Mike Pall
0af3f47ba0
Add allocation sinking and store sinking optimization.
2012-07-02 23:47:12 +02:00
Mike Pall
5d0115ef8d
Add explicit IR_GCSTEP instruction.
2012-07-02 22:42:40 +02:00
Mike Pall
264177b0d0
Use HIOP for XSTORE in SPLIT pass.
2012-07-02 22:37:00 +02:00
Mike Pall
bcd459aa0e
MIPS: Integrate and enable JIT compiler.
2012-03-30 01:36:55 +02:00
