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MIPS: Fix cache flush/sync for JIT-compiled code jump area.

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This commit is contained in:
Mike Pall 2013-02-28 17:52:31 +01:00
parent 3e286c1e72
commit 78c97bc5a1
1 changed files with 1 additions and 0 deletions
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src/lj_asm_mips.h
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@ -71,6 +71,7 @@ static void asm_sparejump_setup(ASMState *as)
memset(mxp+2, 0, MIPS_SPAREJUMP*8);
mxp += MIPS_SPAREJUMP*2;
lua_assert(mxp < as->mctop);
lj_mcode_sync(as->mcbot, mxp);
lj_mcode_commitbot(as->J, mxp);
as->mcbot = mxp;
as->mclim = as->mcbot + MCLIM_REDZONE;