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ARM: Flush instruction cache in assembler backend.

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This commit is contained in:
Mike Pall 2011-05-26 18:04:01 +02:00
parent 4057620bf5
commit 8d4400331d
1 changed files with 14 additions and 1 deletions
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15
src/lj_asm.c
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@ -852,6 +852,19 @@ static uint32_t ir_khash(IRIns *ir)
return hashrot(lo, hi); return hashrot(lo, hi);
} }
/* Flush instruction cache. */
static void asm_cache_flush(MCode *start, MCode *end)
{
VG_INVALIDATE(start, (char *)end-(char *)start);
#if !LJ_TARGET_X86ORX64
#if defined(__GNUC__)
__clear_cache(start, end);
#else
#error "Missing builtin to flush instruction cache"
#endif
#endif
}
/* -- Allocations --------------------------------------------------------- */ /* -- Allocations --------------------------------------------------------- */
static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args); static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args);
@ -1620,7 +1633,7 @@ void lj_asm_trace(jit_State *J, GCtrace *T)
if (!as->loopref) if (!as->loopref)
asm_tail_fixup(as, T->link); /* Note: this may change as->mctop! */ asm_tail_fixup(as, T->link); /* Note: this may change as->mctop! */
T->szmcode = (MSize)((char *)as->mctop - (char *)as->mcp); T->szmcode = (MSize)((char *)as->mctop - (char *)as->mcp);
VG_INVALIDATE(T->mcode, T->szmcode); asm_cache_flush(T->mcode, as->mctop);
} }
#undef IR #undef IR