From 8d4400331d4df7d53a80de6f466e6c7ee3ca9380 Mon Sep 17 00:00:00 2001
From: Mike Pall <mike>
Date: Thu, 26 May 2011 18:04:01 +0200
Subject: [PATCH] ARM: Flush instruction cache in assembler backend.

---
 src/lj_asm.c | 15 ++++++++++++++-
 1 file changed, 14 insertions(+), 1 deletion(-)

diff --git a/src/lj_asm.c b/src/lj_asm.c
index e028ab4f..640b6e15 100644
--- a/src/lj_asm.c
+++ b/src/lj_asm.c
@@ -852,6 +852,19 @@ static uint32_t ir_khash(IRIns *ir)
   return hashrot(lo, hi);
 }
 
+/* Flush instruction cache. */
+static void asm_cache_flush(MCode *start, MCode *end)
+{
+  VG_INVALIDATE(start, (char *)end-(char *)start);
+#if !LJ_TARGET_X86ORX64
+#if defined(__GNUC__)
+  __clear_cache(start, end);
+#else
+#error "Missing builtin to flush instruction cache"
+#endif
+#endif
+}
+
 /* -- Allocations --------------------------------------------------------- */
 
 static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args);
@@ -1620,7 +1633,7 @@ void lj_asm_trace(jit_State *J, GCtrace *T)
   if (!as->loopref)
     asm_tail_fixup(as, T->link);  /* Note: this may change as->mctop! */
   T->szmcode = (MSize)((char *)as->mctop - (char *)as->mcp);
-  VG_INVALIDATE(T->mcode, T->szmcode);
+  asm_cache_flush(T->mcode, as->mctop);
 }
 
 #undef IR