ARM: Add ARM target architecture selection (disabled).

src/Makefile

@@ -51,6 +51,7 @@ CCOPT= -O2 -fomit-frame-pointer
 #
 CCOPT_X86= -march=i686
 CCOPT_X64=
+CCOPT_ARM=
 CCOPT_PPCSPE=
 #
 CCDEBUG=
@@ -223,6 +224,10 @@ ifneq (,$(findstring LJ_TARGET_X86 ,$(TARGET_TESTARCH)))
   TARGET_CCARCH= x86
   TARGET_XCFLAGS+= $(CCOPT_X86)
 else
+ifneq (,$(findstring LJ_TARGET_ARM ,$(TARGET_TESTARCH)))
+  TARGET_CCARCH= arm
+  TARGET_XCFLAGS+= $(CCOPT_ARM)
+else
 ifneq (,$(findstring LJ_TARGET_PPCSPE ,$(TARGET_TESTARCH)))
   TARGET_CCARCH= ppcspe
   TARGET_XCFLAGS+= $(CCOPT_PPCSPE)
@@ -231,6 +236,7 @@ else
 endif
 endif
 endif
+endif
 
 ifneq (,$(PREFIX))
 ifneq (/usr/local,$(PREFIX))

src/buildvm.c

@@ -77,6 +77,9 @@ static int collect_reloc(BuildCtx *ctx, uint8_t *addr, int idx, int type);
 #else
 #include "buildvm_x64.h"
 #endif
+#elif LJ_TARGET_ARM
+#include "../dynasm/dasm_arm.h"
+#include "buildvm_arm.h"
 #elif LJ_TARGET_PPCSPE
 #include "../dynasm/dasm_ppc.h"
 #include "buildvm_ppcspe.h"

src/buildvm_asm.c

@@ -95,7 +95,9 @@ static void emit_asm_wordreloc(BuildCtx *ctx, uint8_t *p, int n,
   uint32_t ins;
   emit_asm_words(ctx, p, n-4);
   ins = *(uint32_t *)(p+n-4);
-#if LJ_TARGET_PPC
+#if LJ_TARGET_ARM
+  UNUSED(sym);  /* NYI */
+#elif LJ_TARGET_PPC
   if ((ins >> 26) == 16) {
     fprintf(ctx->fp, "\t%s %d, %d, %s\n",
 	    (ins & 1) ? "bcl" : "bc", (ins >> 21) & 31, (ins >> 16) & 31, sym);
@@ -113,6 +115,12 @@ static void emit_asm_wordreloc(BuildCtx *ctx, uint8_t *p, int n,
 }
 #endif
 
+#if LJ_TARGET_ARM
+#define ELFASM_PX	"%%"
+#else
+#define ELFASM_PX	"@"
+#endif
+
 /* Emit an assembler label. */
 static void emit_asm_label(BuildCtx *ctx, const char *name, int size, int isfunc)
 {
@@ -121,7 +129,7 @@ static void emit_asm_label(BuildCtx *ctx, const char *name, int size, int isfunc
     fprintf(ctx->fp,
       "\n\t.globl %s\n"
       "\t.hidden %s\n"
-      "\t.type %s, @%s\n"
+      "\t.type %s, " ELFASM_PX "%s\n"
       "\t.size %s, %d\n"
       "%s:\n",
       name, name, name, isfunc ? "function" : "object", name, size, name);
@@ -204,7 +212,7 @@ void emit_asm(BuildCtx *ctx)
   fprintf(ctx->fp, "\n");
   switch (ctx->mode) {
   case BUILD_elfasm:
-    fprintf(ctx->fp, "\t.section .note.GNU-stack,\"\",@progbits\n");
+    fprintf(ctx->fp, "\t.section .note.GNU-stack,\"\"," ELFASM_PX "progbits\n");
 #if LJ_TARGET_PPCSPE
     /* Soft-float ABI + SPE. */
     fprintf(ctx->fp, "\t.gnu_attribute 4, 2\n\t.gnu_attribute 8, 3\n");

src/lib_jit.c

@@ -556,6 +556,8 @@ static uint32_t jit_cpudetect(lua_State *L)
     luaL_error(L, "CPU does not support SSE2 (recompile without -DLUAJIT_CPU_SSE2)");
 #endif
 #endif
+#elif LJ_TARGET_ARM
+  /* NYI */
 #elif LJ_TARGET_PPC
   /* Nothing to do. */
 #else

src/lj_arch.h

@@ -17,10 +17,12 @@
 #define LUAJIT_ARCH_x86		1
 #define LUAJIT_ARCH_X64		2
 #define LUAJIT_ARCH_x64		2
-#define LUAJIT_ARCH_PPC		3
+#define LUAJIT_ARCH_ARM		3
-#define LUAJIT_ARCH_ppc		3
+#define LUAJIT_ARCH_arm		3
-#define LUAJIT_ARCH_PPCSPE	4
+#define LUAJIT_ARCH_PPC		4
-#define LUAJIT_ARCH_ppcspe	4
+#define LUAJIT_ARCH_ppc		4
+#define LUAJIT_ARCH_PPCSPE	5
+#define LUAJIT_ARCH_ppcspe	5
 
 /* Target OS. */
 #define LUAJIT_OS_OTHER		0
@@ -37,6 +39,8 @@
 #define LUAJIT_TARGET	LUAJIT_ARCH_X86
 #elif defined(__x86_64__) || defined(__x86_64) || defined(_M_X64) || defined(_M_AMD64)
 #define LUAJIT_TARGET	LUAJIT_ARCH_X64
+#elif defined(__arm__) || defined(__arm) || defined(__ARM__) || defined(__ARM)
+#define LUAJIT_TARGET	LUAJIT_ARCH_ARM
 #elif defined(__ppc__) || defined(__ppc) || defined(__PPC__) || defined(__PPC) || defined(__powerpc__) || defined(__powerpc) || defined(__POWERPC__) || defined(__POWERPC) || defined(_M_PPC)
 #ifdef __NO_FPRS__
 #define LUAJIT_TARGET	LUAJIT_ARCH_PPCSPE
@@ -117,6 +121,22 @@
 #define LJ_TARGET_MASKSHIFT	1
 #define LJ_TARGET_MASKROT	1
 
+#elif LUAJIT_TARGET == LUAJIT_ARCH_ARM
+
+#error "No support for ARM CPUs (yet)"
+#define LJ_ARCH_NAME		"arm"
+#define LJ_ARCH_BITS		32
+#define LJ_ARCH_ENDIAN		LUAJIT_LE
+#define LJ_ARCH_HASFPU		0
+#define LJ_ABI_SOFTFP		1
+#define LJ_ABI_EABI		1
+#define LJ_TARGET_ARM		1
+#define LJ_TARGET_EHRETREG	0
+#define LJ_TARGET_MASKSHIFT	0
+#define LJ_TARGET_MASKROT	1
+#define LJ_ARCH_NOFFI		1
+#define LJ_ARCH_NOJIT		1
+
 #elif LUAJIT_TARGET == LUAJIT_ARCH_PPC
 
 #error "No support for plain PowerPC CPUs (yet)"
@@ -150,7 +170,7 @@
 #if __GNUC__ < 4
 #error "Need at least GCC 4.0 or newer"
 #endif
-#elif LJ_TARGET_PPC
+#elif LJ_TARGET_ARM || LJ_TARGET_PPC
 #if (__GNUC__ < 4) || ((__GNUC__ == 4) && __GNUC_MINOR__ < 3)
 #error "Need at least GCC 4.3 or newer"
 #endif
@@ -163,7 +183,17 @@
 
 /* Check target-specific constraints. */
 #ifndef _BUILDVM_H
-#if LJ_TARGET_PPC
+#if LJ_TARGET_ARM
+#if defined(__ARMEB__)
+#error "No support for big-endian ARM"
+#endif
+#if defined(__thumb__) || defined(__thumb2__)
+#error "No support for Thumb instruction set (yet)"
+#endif
+#if !__ARM_EABI__
+#error "Only ARM EABI is supported"
+#endif
+#elif LJ_TARGET_PPC
 #if defined(_SOFT_FLOAT) || defined(_SOFT_DOUBLE)
 #error "No support for PowerPC CPUs without double-precision FPU"
 #endif

src/lj_err.c

@@ -526,7 +526,7 @@ static void *err_unwind(lua_State *L, void *stopcf, int errcode)
 
 /* -- External frame unwinding -------------------------------------------- */
 
-#if defined(__GNUC__)
+#if defined(__GNUC__) && !LJ_TARGET_ARM
 
 #include <unwind.h>
 

src/lj_frame.h

@@ -90,6 +90,17 @@ enum {
 #define CFRAME_SIZE_JIT		(CFRAME_SIZE + 16)
 #define CFRAME_SHIFT_MULTRES	0
 #endif
+#elif LJ_TARGET_ARM
+/* NYI: Dummy definitions for now. */
+#define CFRAME_OFS_ERRF		28
+#define CFRAME_OFS_NRES		24
+#define CFRAME_OFS_PREV		20
+#define CFRAME_OFS_L		16
+#define CFRAME_OFS_PC		12
+#define CFRAME_OFS_MULTRES	8
+#define CFRAME_SIZE		64
+#define CFRAME_SIZE_JIT		CFRAME_SIZE
+#define CFRAME_SHIFT_MULTRES	3
 #elif LJ_TARGET_PPCSPE
 #define CFRAME_OFS_ERRF		28
 #define CFRAME_OFS_NRES		24