mirror of
https://github.com/LuaJIT/LuaJIT.git
synced 2025-02-07 15:14:08 +00:00
474 lines
14 KiB
C
474 lines
14 KiB
C
/*
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** ARM64 instruction emitter.
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** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
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**
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** Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
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** Sponsored by Cisco Systems, Inc.
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*/
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/* -- Constant encoding --------------------------------------------------- */
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static uint64_t get_k64val(ASMState *as, IRRef ref)
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{
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IRIns *ir = IR(ref);
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if (ir->o == IR_KINT64) {
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return ir_kint64(ir)->u64;
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} else if (ir->o == IR_KGC) {
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return (uint64_t)ir_kgc(ir);
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} else if (ir->o == IR_KPTR || ir->o == IR_KKPTR) {
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return (uint64_t)ir_kptr(ir);
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} else {
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lj_assertA(ir->o == IR_KINT || ir->o == IR_KNULL,
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"bad 64 bit const IR op %d", ir->o);
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return (uint32_t)ir->i; /* Zero-extended. */
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}
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}
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/* Encode constant in K12 format for data processing instructions. */
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static uint32_t emit_isk12(int64_t n)
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{
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uint64_t k = n < 0 ? ~(uint64_t)n+1u : (uint64_t)n;
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uint32_t m = n < 0 ? 0x40000000 : 0;
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if (k < 0x1000) {
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return (uint32_t)(A64I_K12|m|A64F_U12(k));
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} else if ((k & 0xfff000) == k) {
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return (uint32_t)(A64I_K12|m|0x400000|A64F_U12(k>>12));
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}
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return 0;
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}
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#define emit_clz64(n) (lj_fls64(n)^63)
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#define emit_ctz64(n) lj_ffs64(n)
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/* Encode constant in K13 format for logical data processing instructions. */
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static uint32_t emit_isk13(uint64_t n, int is64)
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{
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/* Thanks to: https://dougallj.wordpress.com/2021/10/30/ */
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int rot, ones, size, immr, imms;
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if (!is64) n = ((uint64_t)n << 32) | (uint32_t)n;
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if ((n+1u) <= 1u) return 0; /* Neither all-zero nor all-ones are allowed. */
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rot = (n & (n+1u)) ? emit_ctz64(n & (n+1u)) : 64;
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n = lj_ror(n, rot & 63);
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ones = emit_ctz64(~n);
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size = emit_clz64(n) + ones;
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if (lj_ror(n, size & 63) != n) return 0; /* Non-repeating? */
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immr = -rot & (size - 1);
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imms = (-(size << 1) | (ones - 1)) & 63;
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return A64I_K13 | A64F_IMMR(immr | (size & 64)) | A64F_IMMS(imms);
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}
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static uint32_t emit_isfpk64(uint64_t n)
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{
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uint64_t etop9 = ((n >> 54) & 0x1ff);
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if ((n << 16) == 0 && (etop9 == 0x100 || etop9 == 0x0ff)) {
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return (uint32_t)(((n >> 48) & 0x7f) | ((n >> 56) & 0x80));
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}
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return ~0u;
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}
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static uint32_t emit_isfpmovi(uint64_t n)
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{
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/* Is every byte either 0x00 or 0xff? */
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if ((n & U64x(01010101,01010101)) * 0xff != n) return 0;
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/* Form 8-bit value by taking one bit from each byte. */
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n &= U64x(80402010,08040201);
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n = (n * U64x(01010101,01010101)) >> 56;
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/* Split into the format expected by movi. */
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return ((n & 0xe0) << 6) | 0x700 | (n & 0x1f);
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}
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/* -- Emit basic instructions --------------------------------------------- */
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static void emit_dnma(ASMState *as, A64Ins ai, Reg rd, Reg rn, Reg rm, Reg ra)
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{
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*--as->mcp = ai | A64F_D(rd) | A64F_N(rn) | A64F_M(rm) | A64F_A(ra);
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}
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static void emit_dnm(ASMState *as, A64Ins ai, Reg rd, Reg rn, Reg rm)
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{
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*--as->mcp = ai | A64F_D(rd) | A64F_N(rn) | A64F_M(rm);
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}
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static void emit_dm(ASMState *as, A64Ins ai, Reg rd, Reg rm)
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{
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*--as->mcp = ai | A64F_D(rd) | A64F_M(rm);
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}
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static void emit_dn(ASMState *as, A64Ins ai, Reg rd, Reg rn)
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{
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*--as->mcp = ai | A64F_D(rd) | A64F_N(rn);
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}
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static void emit_nm(ASMState *as, A64Ins ai, Reg rn, Reg rm)
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{
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*--as->mcp = ai | A64F_N(rn) | A64F_M(rm);
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}
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static void emit_d(ASMState *as, A64Ins ai, Reg rd)
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{
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*--as->mcp = ai | A64F_D(rd);
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}
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static void emit_dl(ASMState *as, A64Ins ai, Reg rd, uint32_t l)
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{
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*--as->mcp = ai | A64F_D(rd) | A64F_S19(l >> 2);
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}
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static void emit_n(ASMState *as, A64Ins ai, Reg rn)
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{
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*--as->mcp = ai | A64F_N(rn);
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}
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static int emit_checkofs(A64Ins ai, int64_t ofs)
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{
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int scale = (ai >> 30) & 3;
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if (ofs < 0 || (ofs & ((1<<scale)-1))) {
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return (ofs >= -256 && ofs <= 255) ? -1 : 0;
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} else {
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return (ofs < (4096<<scale)) ? 1 : 0;
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}
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}
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static LJ_AINLINE uint32_t emit_lso_pair_candidate(A64Ins ai, int ofs, int sc)
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{
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if (ofs >= 0) {
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return ai | A64F_U12(ofs>>sc); /* Subsequent lj_ror checks ofs. */
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} else if (ofs >= -256) {
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return (ai^A64I_LS_U) | A64F_S9(ofs & 0x1ff);
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} else {
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return A64F_D(31); /* Will mismatch prev. */
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}
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}
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static void emit_lso(ASMState *as, A64Ins ai, Reg rd, Reg rn, int64_t ofs64)
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{
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int ot = emit_checkofs(ai, ofs64), sc = (ai >> 30) & 3, ofs = (int)ofs64;
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lj_assertA(ot, "load/store offset %d out of range", ofs);
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/* Combine LDR/STR pairs to LDP/STP. */
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if ((sc == 2 || sc == 3) &&
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(!(ai & 0x400000) || rd != rn) &&
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as->mcp != as->mcloop) {
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uint32_t prev = *as->mcp & ~A64F_D(31);
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int ofsm = ofs - (1<<sc), ofsp = ofs + (1<<sc);
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A64Ins aip;
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if (prev == emit_lso_pair_candidate(ai | A64F_N(rn), ofsm, sc)) {
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aip = (A64F_A(rd) | A64F_D(*as->mcp & 31));
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} else if (prev == emit_lso_pair_candidate(ai | A64F_N(rn), ofsp, sc)) {
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aip = (A64F_D(rd) | A64F_A(*as->mcp & 31));
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ofsm = ofs;
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} else {
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goto nopair;
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}
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if (lj_ror((unsigned int)ofsm + (64u<<sc), sc) <= 127u) {
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*as->mcp = aip | A64F_N(rn) | (((ofsm >> sc) & 0x7f) << 15) |
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(ai ^ ((ai == A64I_LDRx || ai == A64I_STRx) ? 0x50000000 : 0x90000000));
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return;
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}
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}
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nopair:
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if (ot == 1)
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*--as->mcp = ai | A64F_D(rd) | A64F_N(rn) | A64F_U12(ofs >> sc);
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else
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*--as->mcp = (ai^A64I_LS_U) | A64F_D(rd) | A64F_N(rn) | A64F_S9(ofs & 0x1ff);
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}
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/* -- Emit loads/stores --------------------------------------------------- */
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/* Prefer rematerialization of BASE/L from global_State over spills. */
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#define emit_canremat(ref) ((ref) <= REF_BASE)
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/* Try to find a one-step delta relative to other consts. */
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static int emit_kdelta(ASMState *as, Reg rd, uint64_t k, int is64)
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{
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RegSet work = (~as->freeset & RSET_GPR) | RID2RSET(RID_GL);
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while (work) {
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Reg r = rset_picktop(work);
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IRRef ref = regcost_ref(as->cost[r]);
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lj_assertA(r != rd, "dest reg %d not free", rd);
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if (ref < REF_TRUE) {
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uint64_t kx = ra_iskref(ref) ? (uint64_t)ra_krefk(as, ref) :
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get_k64val(as, ref);
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int64_t delta = (int64_t)(k - kx);
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if (!is64) delta = (int64_t)(int32_t)delta; /* Sign-extend. */
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if (delta == 0) {
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emit_dm(as, is64|A64I_MOVw, rd, r);
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return 1;
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} else {
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uint32_t k12 = emit_isk12(delta < 0 ? (int64_t)(~(uint64_t)delta+1u) : delta);
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if (k12) {
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emit_dn(as, (delta < 0 ? A64I_SUBw : A64I_ADDw)^is64^k12, rd, r);
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return 1;
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}
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/* Do other ops or multi-step deltas pay off? Probably not.
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** E.g. XOR rarely helps with pointer consts.
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*/
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}
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}
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rset_clear(work, r);
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}
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return 0; /* Failed. */
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}
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#define glofs(as, k) \
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((intptr_t)((uintptr_t)(k) - (uintptr_t)&J2GG(as->J)->g))
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#define mcpofs(as, k) \
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((intptr_t)((uintptr_t)(k) - (uintptr_t)(as->mcp - 1)))
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#define checkmcpofs(as, k) \
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(A64F_S_OK(mcpofs(as, k)>>2, 19))
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/* Try to form a const as ADR or ADRP or ADRP + ADD. */
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static int emit_kadrp(ASMState *as, Reg rd, uint64_t k)
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{
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A64Ins ai = A64I_ADR;
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int64_t ofs = mcpofs(as, k);
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if (!A64F_S_OK((uint64_t)ofs, 21)) {
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uint64_t kpage = k & ~0xfffull;
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MCode *adrp = as->mcp - 1 - (k != kpage);
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ofs = (int64_t)(kpage - ((uint64_t)adrp & ~0xfffull)) >> 12;
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if (!A64F_S_OK(ofs, 21))
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return 0; /* Failed. */
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if (k != kpage)
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emit_dn(as, (A64I_ADDx^A64I_K12)|A64F_U12(k - kpage), rd, rd);
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ai = A64I_ADRP;
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}
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emit_dl(as, ai|(((uint32_t)ofs&3)<<29), rd, ofs);
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return 1;
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}
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static void emit_loadk(ASMState *as, Reg rd, uint64_t u64)
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{
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int zeros = 0, ones = 0, neg, lshift = 0;
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int is64 = (u64 >> 32) ? A64I_X : 0, i = is64 ? 4 : 2;
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/* Count non-homogeneous 16 bit fragments. */
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while (--i >= 0) {
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uint32_t frag = (u64 >> i*16) & 0xffff;
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zeros += (frag != 0);
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ones += (frag != 0xffff);
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}
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neg = ones < zeros; /* Use MOVN if it pays off. */
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if ((neg ? ones : zeros) > 1) { /* Need 2+ ins. Try 1 ins encodings. */
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uint32_t k13 = emit_isk13(u64, is64);
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if (k13) {
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emit_dn(as, (is64|A64I_ORRw)^k13, rd, RID_ZERO);
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return;
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}
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if (emit_kdelta(as, rd, u64, is64)) {
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return;
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}
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if (emit_kadrp(as, rd, u64)) { /* Either 1 or 2 ins. */
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return;
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}
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}
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if (neg) {
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u64 = ~u64;
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if (!is64) u64 = (uint32_t)u64;
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}
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if (u64) {
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/* Find first/last fragment to be filled. */
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int shift = (63-emit_clz64(u64)) & ~15;
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lshift = emit_ctz64(u64) & ~15;
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for (; shift > lshift; shift -= 16) {
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uint32_t frag = (u64 >> shift) & 0xffff;
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if (frag == 0) continue; /* Will be correctly filled by MOVN/MOVZ. */
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if (neg) frag ^= 0xffff; /* MOVK requires the original value. */
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emit_d(as, is64 | A64I_MOVKw | A64F_U16(frag) | A64F_LSL16(shift), rd);
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}
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}
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/* But MOVN needs an inverted value. */
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emit_d(as, is64 | (neg ? A64I_MOVNw : A64I_MOVZw) |
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A64F_U16((u64 >> lshift) & 0xffff) | A64F_LSL16(lshift), rd);
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}
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/* Load a 32 bit constant into a GPR. */
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#define emit_loadi(as, rd, i) emit_loadk(as, rd, (uint32_t)i)
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/* Load a 64 bit constant into a GPR. */
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#define emit_loadu64(as, rd, i) emit_loadk(as, rd, i)
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static Reg ra_allock(ASMState *as, intptr_t k, RegSet allow);
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/* Get/set from constant pointer. */
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static void emit_lsptr(ASMState *as, A64Ins ai, Reg r, void *p)
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{
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Reg base = RID_GL;
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int64_t ofs = glofs(as, p);
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if (emit_checkofs(ai, ofs)) {
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/* GL + offset, might subsequently fuse to LDP/STP. */
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} else if (ai == A64I_LDRx && checkmcpofs(as, p)) {
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/* IP + offset is cheaper than allock, but address must be in range. */
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emit_dl(as, A64I_LDRLx, r, mcpofs(as, p));
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return;
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} else { /* Split up into base reg + offset. */
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int64_t i64 = i64ptr(p);
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base = ra_allock(as, (i64 & ~0x7fffull), rset_exclude(RSET_GPR, r));
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ofs = i64 & 0x7fffull;
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}
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emit_lso(as, ai, r, base, ofs);
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}
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/* Load 64 bit IR constant into register. */
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static void emit_loadk64(ASMState *as, Reg r, IRIns *ir)
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{
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const uint64_t *k = &ir_k64(ir)->u64;
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int64_t ofs;
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if (r >= RID_MAX_GPR) {
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uint32_t fpk = emit_isfpk64(*k);
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if (fpk != ~0u) {
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emit_d(as, A64I_FMOV_DI | A64F_FP8(fpk), (r & 31));
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return;
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} else if ((fpk = emit_isfpmovi(*k))) {
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emit_d(as, A64I_MOVI_DI | (fpk << 5), (r & 31));
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return;
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}
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}
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ofs = glofs(as, k);
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if (emit_checkofs(A64I_LDRx, ofs)) {
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emit_lso(as, r >= RID_MAX_GPR ? A64I_LDRd : A64I_LDRx,
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(r & 31), RID_GL, ofs);
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} else if (checkmcpofs(as, k)) {
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emit_dl(as, r >= RID_MAX_GPR ? A64I_LDRLd : A64I_LDRLx,
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(r & 31), mcpofs(as, k));
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} else {
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if (r >= RID_MAX_GPR) {
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emit_dn(as, A64I_FMOV_D_R, (r & 31), RID_TMP);
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r = RID_TMP;
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}
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emit_loadu64(as, r, *k);
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}
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}
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/* Get/set global_State fields. */
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#define emit_getgl(as, r, field) \
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emit_lsptr(as, A64I_LDRx, (r), (void *)&J2G(as->J)->field)
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#define emit_setgl(as, r, field) \
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emit_lsptr(as, A64I_STRx, (r), (void *)&J2G(as->J)->field)
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/* Trace number is determined from pc of exit instruction. */
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#define emit_setvmstate(as, i) UNUSED(i)
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/* -- Emit control-flow instructions -------------------------------------- */
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/* Label for internal jumps. */
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typedef MCode *MCLabel;
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/* Return label pointing to current PC. */
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#define emit_label(as) ((as)->mcp)
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static void emit_cond_branch(ASMState *as, A64CC cond, MCode *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = target - p;
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lj_assertA(A64F_S_OK(delta, 19), "branch target out of range");
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*p = A64I_BCC | A64F_S19(delta) | cond;
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}
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static void emit_branch(ASMState *as, A64Ins ai, MCode *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = target - p;
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lj_assertA(A64F_S_OK(delta, 26), "branch target out of range");
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*p = ai | A64F_S26(delta);
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}
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static void emit_tnb(ASMState *as, A64Ins ai, Reg r, uint32_t bit, MCode *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = target - p;
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lj_assertA(bit < 63, "bit number out of range");
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lj_assertA(A64F_S_OK(delta, 14), "branch target out of range");
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if (bit > 31) ai |= A64I_X;
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*p = ai | A64F_BIT(bit & 31) | A64F_S14(delta) | r;
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}
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static void emit_cnb(ASMState *as, A64Ins ai, Reg r, MCode *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = target - p;
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lj_assertA(A64F_S_OK(delta, 19), "branch target out of range");
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*p = ai | A64F_S19(delta) | r;
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}
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#define emit_jmp(as, target) emit_branch(as, A64I_B, (target))
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static void emit_call(ASMState *as, ASMFunction target)
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{
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MCode *p = --as->mcp;
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#if LJ_ABI_PAUTH
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char *targetp = ptrauth_auth_data((char *)target,
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ptrauth_key_function_pointer, 0);
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#else
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char *targetp = (char *)target;
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#endif
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ptrdiff_t delta = targetp - (char *)p;
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if (A64F_S_OK(delta>>2, 26)) {
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*p = A64I_BL | A64F_S26(delta>>2);
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} else { /* Target out of range: need indirect call. But don't use R0-R7. */
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Reg r = ra_allock(as, i64ptr(target),
|
|
RSET_RANGE(RID_X8, RID_MAX_GPR)-RSET_FIXED);
|
|
*p = A64I_BLR_AUTH | A64F_N(r);
|
|
}
|
|
}
|
|
|
|
/* -- Emit generic operations --------------------------------------------- */
|
|
|
|
/* Generic move between two regs. */
|
|
static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
|
|
{
|
|
if (dst >= RID_MAX_GPR) {
|
|
emit_dn(as, irt_isnum(ir->t) ? A64I_FMOV_D : A64I_FMOV_S,
|
|
(dst & 31), (src & 31));
|
|
return;
|
|
}
|
|
if (as->mcp != as->mcloop) { /* Swap early registers for loads/stores. */
|
|
MCode ins = *as->mcp, swp = (src^dst);
|
|
if ((ins & 0xbf800000) == 0xb9000000) {
|
|
if (!((ins ^ (dst << 5)) & 0x000003e0))
|
|
*as->mcp = ins ^ (swp << 5); /* Swap N in load/store. */
|
|
if (!(ins & 0x00400000) && !((ins ^ dst) & 0x0000001f))
|
|
*as->mcp = ins ^ swp; /* Swap D in store. */
|
|
}
|
|
}
|
|
emit_dm(as, A64I_MOVx, dst, src);
|
|
}
|
|
|
|
/* Generic load of register with base and (small) offset address. */
|
|
static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
|
|
{
|
|
if (r >= RID_MAX_GPR)
|
|
emit_lso(as, irt_isnum(ir->t) ? A64I_LDRd : A64I_LDRs, (r & 31), base, ofs);
|
|
else
|
|
emit_lso(as, irt_is64(ir->t) ? A64I_LDRx : A64I_LDRw, r, base, ofs);
|
|
}
|
|
|
|
/* Generic store of register with base and (small) offset address. */
|
|
static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
|
|
{
|
|
if (r >= RID_MAX_GPR)
|
|
emit_lso(as, irt_isnum(ir->t) ? A64I_STRd : A64I_STRs, (r & 31), base, ofs);
|
|
else
|
|
emit_lso(as, irt_is64(ir->t) ? A64I_STRx : A64I_STRw, r, base, ofs);
|
|
}
|
|
|
|
/* Emit an arithmetic operation with a constant operand. */
|
|
static void emit_opk(ASMState *as, A64Ins ai, Reg dest, Reg src,
|
|
int32_t i, RegSet allow)
|
|
{
|
|
uint32_t k = emit_isk12(i);
|
|
if (k)
|
|
emit_dn(as, ai^k, dest, src);
|
|
else
|
|
emit_dnm(as, ai, dest, src, ra_allock(as, i, allow));
|
|
}
|
|
|
|
/* Add offset to pointer. */
|
|
static void emit_addptr(ASMState *as, Reg r, int32_t ofs)
|
|
{
|
|
if (ofs)
|
|
emit_opk(as, ofs < 0 ? A64I_SUBx : A64I_ADDx, r, r,
|
|
ofs < 0 ? (int32_t)(~(uint32_t)ofs+1u) : ofs,
|
|
rset_exclude(RSET_GPR, r));
|
|
}
|
|
|
|
#define emit_spsub(as, ofs) emit_addptr(as, RID_SP, -(ofs))
|
|
|