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190 lines
5.3 KiB
C
190 lines
5.3 KiB
C
/*
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** Definitions for S390 CPUs.
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** Copyright (C) 2005-2016 Mike Pall. See Copyright Notice in luajit.h
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*/
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#ifndef _LJ_TARGET_S390_H
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#define _LJ_TARGET_S390_H
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/* -- Registers IDs ------------------------------------------------------- */
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#define GPRDEF(_) \
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_(R0) _(R1) _(R2) _(R3) _(R4) _(R5) _(R6) _(R7) \
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_(R8) _(R9) _(R10) _(R11) _(R12) _(R13) _(R14) _R(15) \
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#if LJ_SOFTFP
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#define FPRDEF(_)
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#else
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#define FPRDEF(_) \
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_(F0) _(F1) _(F2) _(F3) \
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_(F4) _(F5) _(F6) _(F7) \
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_(F8) _(F9) _(F10) _(F11) \
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_(F12) _(F13) _(F14) _(F15)
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#endif
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#define VRIDDEF(_)
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#define RIDENUM(name) RID_##name,
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enum {
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GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
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FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
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RID_MAX,
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RID_TMP = RID_LR,
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/* Calling conventions. */
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RID_RET = RID_R0,
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RID_RETLO = RID_R0,
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RID_RETHI = RID_R1,
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#if LJ_SOFTFP
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RID_FPRET = RID_R0,
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#else
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RID_FPRET = RID_D0,
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#endif
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/* These definitions must match with the *.dasc file(s): */
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RID_BASE = RID_R9, /* Interpreter BASE. */
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RID_LPC = RID_R6, /* Interpreter PC. */
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RID_DISPATCH = RID_R7, /* Interpreter DISPATCH table. */
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RID_LREG = RID_R8, /* Interpreter L. */
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/* Register ranges [min, max) and number of registers. */
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RID_MIN_GPR = RID_R0,
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RID_MAX_GPR = RID_PC+1,
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RID_MIN_FPR = RID_MAX_GPR,
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#if LJ_SOFTFP
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RID_MAX_FPR = RID_MIN_FPR,
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#else
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RID_MAX_FPR = RID_D15+1,
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#endif
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RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
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RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR
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};
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#define RID_NUM_KREF RID_NUM_GPR
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#define RID_MIN_KREF RID_R0
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/* -- Register sets ------------------------------------------------------- */
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/* Make use of all registers, except sp, lr and pc. */
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#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_R12+1))
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#define RSET_GPREVEN \
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(RID2RSET(RID_R0)|RID2RSET(RID_R2)|RID2RSET(RID_R4)|RID2RSET(RID_R6)| \
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RID2RSET(RID_R8)|RID2RSET(RID_R10))
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#define RSET_GPRODD \
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(RID2RSET(RID_R1)|RID2RSET(RID_R3)|RID2RSET(RID_R5)|RID2RSET(RID_R7)| \
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RID2RSET(RID_R9)|RID2RSET(RID_R11))
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#if LJ_SOFTFP
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#define RSET_FPR 0
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#else
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#define RSET_FPR (RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR))
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#endif
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#define RSET_ALL (RSET_GPR|RSET_FPR)
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#define RSET_INIT RSET_ALL
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/* ABI-specific register sets. lr is an implicit scratch register. */
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#define RSET_SCRATCH_GPR_ (RSET_RANGE(RID_R0, RID_R3+1)|RID2RSET(RID_R12))
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#ifdef __APPLE__
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#define RSET_SCRATCH_GPR (RSET_SCRATCH_GPR_|RID2RSET(RID_R9))
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#else
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#define RSET_SCRATCH_GPR RSET_SCRATCH_GPR_
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#endif
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#if LJ_SOFTFP
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#define RSET_SCRATCH_FPR 0
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#else
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#define RSET_SCRATCH_FPR (RSET_RANGE(RID_D0, RID_D7+1))
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#endif
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#define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
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#define REGARG_FIRSTGPR RID_R0
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#define REGARG_LASTGPR RID_R3
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#define REGARG_NUMGPR 4
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#if LJ_ABI_SOFTFP
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#define REGARG_FIRSTFPR 0
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#define REGARG_LASTFPR 0
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#define REGARG_NUMFPR 0
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#else
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#define REGARG_FIRSTFPR RID_D0
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#define REGARG_LASTFPR RID_D7
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#define REGARG_NUMFPR 8
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#endif
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/* -- Spill slots --------------------------------------------------------- */
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/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
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**
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** SPS_FIXED: Available fixed spill slots in interpreter frame.
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** This definition must match with the *.dasc file(s).
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**
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** SPS_FIRST: First spill slot for general use. Reserve min. two 32 bit slots.
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*/
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#define SPS_FIXED 2
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#define SPS_FIRST 2
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#define SPOFS_TMP 0
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#define sps_scale(slot) (4 * (int32_t)(slot))
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#define sps_align(slot) (((slot) - SPS_FIXED + 1) & ~1)
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/* -- Exit state ---------------------------------------------------------- */
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/* This definition must match with the *.dasc file(s). */
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typedef struct {
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#if !LJ_SOFTFP
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lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
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#endif
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int32_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
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int32_t spill[256]; /* Spill slots. */
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} ExitState;
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/* PC after instruction that caused an exit. Used to find the trace number. */
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#define EXITSTATE_PCREG RID_PC
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/* Highest exit + 1 indicates stack check. */
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#define EXITSTATE_CHECKEXIT 1
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#define EXITSTUB_SPACING 4
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#define EXITSTUBS_PER_GROUP 32
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/* -- Instructions -------------------------------------------------------- */
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/* Instruction fields. */
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#define ARMF_CC(ai, cc) (((ai) ^ ARMI_CCAL) | ((cc) << 28))
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#define ARMF_N(r) ((r) << 16)
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#define ARMF_D(r) ((r) << 12)
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#define ARMF_S(r) ((r) << 8)
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#define ARMF_M(r) (r)
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#define ARMF_SH(sh, n) (((sh) << 5) | ((n) << 7))
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#define ARMF_RSH(sh, r) (0x10 | ((sh) << 5) | ARMF_S(r))
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typedef enum S390xIns {
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S390I_SR = 0x1B00000000000000,
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S390I_AR = 0x1A00000000000000,
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S390I_NR = 0x1400000000000000,
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S390I_XR = 0x1700000000000000,
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S390I_MR = 0x1C00000000000000,
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S390I_LR = 0x1800000000000000,
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S390I_C = 0x5900000000000000,
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S390I_LH = 0x4800000000000000,
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S390I_BASR = 0x0D00000000000000,
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S390I_MVCL = 0x0e00000000000000,
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S390I_ST = 0x5000000000000000,
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S390I_TM = 0x9100000000000000,
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S390I_MP = 0xbd00009000000000,
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S390I_CLR = 0x1500000000000000,
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} S390xIns;
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typedef enum S390xShift {
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S390SH_SLL, S390SH_SRL, S390SH_SRA
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} S390xShift;
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/* S390x condition codes. */
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typedef enum S390xCC {
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/* Z- Zero , LZ - Less thena Zero , GZ - Greater than Zero
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O - Overflow , NZ - Not Zero , ZC - Zero with carry
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NZC - No Zero with carry , ZNC - Zero with No Carry
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EQ - Equal , NE - Not Equal , LO - Loq , HI - High
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*/
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CC_Z , CC_LZ , CC_GZ , CC_O ,
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CC_NZ , CC_ZC , CC_NZC ,
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CC_ZNC , CC_EQ , CC_NE , CC_LO , CC_HI
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} S390xCC;
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#endif
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