preetikhorjuvenkar
00c4e1c85d
Changed the year from 2016 to 2017
2018-02-14 10:06:52 +00:00
preetikhorjuvenkar
04375136ff
Merge branch 'v2.1' of https://github.com/LuaJIT/LuaJIT into v2.1
2018-02-14 05:23:54 +00:00
Mike Pall
0bf46e1edf
Merge branch 'master' into v2.1
2018-01-29 13:19:30 +01:00
Mike Pall
d4ee803427
Fix GCC 7 -Wimplicit-fallthrough warnings.
2018-01-29 13:06:13 +01:00
Mike Pall
6a2d8b0b4d
Merge branch 'master' into v2.1
2017-09-20 19:42:34 +02:00
Mike Pall
0c0e7b168e
DynASM/x86: Fix potential REL_A overflow.
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Thanks to Joshua Haberman.
2017-09-20 19:39:50 +02:00
Mike Pall
a9740d9edb
DynASM: Fix warning.
2017-03-08 21:59:14 +01:00
Michael Munday
72ba386d14
Various minor style changes.
2017-01-31 16:38:33 -05:00
Michael Munday
09017733b8
Re-arrange instruction encodings so they are in alphabetical order.
2017-01-31 15:42:48 -05:00
Michael Munday
7352e706fb
Use real encoding names for extended mnemonics.
2017-01-31 15:30:54 -05:00
Michael Munday
60bc2fad2d
Sort instructions in alphabetical order.
2017-01-31 15:23:03 -05:00
Mike Pall
71ff7ef8a7
Merge branch 'master' into v2.1
2017-01-17 12:41:05 +01:00
Mike Pall
b93a1dd0c8
Bump copyright date to 2017.
2017-01-17 12:35:03 +01:00
Michael Munday
a3bb1cee5d
Add and use branch on count instructions where possible.
2017-01-11 16:38:35 -05:00
ketank-new
db99c31890
Added example for 'TM' instruction
2017-01-11 17:04:09 +05:30
Michael Munday
21655cf90b
Add remaining (useful) SI instructions to DynASM.
2017-01-10 12:52:02 -05:00
Michael Munday
a038a08189
Fix SI (tm) action parsing.
2017-01-10 11:37:25 -05:00
Michael Munday
a8562b7f34
Allow displacements to be used directly without register values.
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Allows sllg r1, r1, 3(r0,r0) to be written as sllg r1, r1, 3.
2017-01-10 10:50:41 -05:00
Michael Munday
443814b6b3
Add more convert to/from fixed instructions to DynASM.
2017-01-06 11:16:04 -05:00
niravthakkar
206c650689
Updated the memory parsing
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The order matters here, so just moved displacement check to end
2017-01-05 14:48:09 +05:30
niravthakkar
7aae451d93
Reverting the changes, as its breaking the build
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The above expression works on CLI, but its failing here, not sure whats going wrong , Please let me know your comments on it
2017-01-04 18:15:57 +05:30
niravthakkar
1fe2176241
Updated memory parsing
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The values of base and index registers have been passed as 0, if only displacement is passed
the displacement is assumed to be alphanumeric (since label might be used)
2017-01-04 17:43:53 +05:30
niravthakkar
6bbfa48b93
Updated the memory parsing
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It accepts 2 registers, without the displacement
2017-01-04 16:20:56 +05:30
ketank-new
47012cea2f
Added example for RX-f based instruction mode
2017-01-03 17:08:30 +05:30
niravthakkar
b84dd8e65d
Added couple of instructions required by test-case
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maeb(RXF) and cegbra(RRF-e) have been added
2017-01-03 16:16:29 +05:30
niravthakkar
dd6ecfa73d
Added SIY addressing mode support
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Added SIY add mode, and Updated the number of parameters for few of the instructions of RS-a mode
2017-01-03 15:51:23 +05:30
Michael Munday
12602d2a1f
Fix for DynASM buffer overflow.
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Need to include all actions with arguments against MAXSECPOS.
2016-12-29 16:50:58 -05:00
ketank-new
4853da820a
Added test example for RXE mode
2016-12-21 18:43:25 +05:30
Michael Munday
419869b20e
Fixes for DynASM.
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* s/hle/nle/
* Fix RRF-b encoding (didbr instruction)
2016-12-20 14:53:31 -05:00
Michael Munday
5076a3ee2e
Fix some DynASM instructions.
2016-12-20 09:27:40 -05:00
niravthakkar
28b6fe8759
Updated encoding for instructions
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Have replaced the characters used for encoding with their respective addressing modes
2016-12-20 17:50:29 +05:30
Michael Munday
0d442ec688
Add some more instructions to DynASM.
2016-12-19 14:21:24 -05:00
Michael Munday
bee112d431
Add support for global short assignments.
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In other words 'a = 1' now works.
2016-12-16 17:23:46 -05:00
ketank-new
b7c4e4b3d6
Added rre instruction format example
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example includes instruction fidr
2016-12-15 13:51:46 +05:30
Michael Munday
f79a6f3f0b
Add support for clm instruction.
2016-12-14 21:16:30 -05:00
Michael Munday
ef3ff100f2
Fix decoding of REL_EXT.
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REL_EXT has an argument which wasn't being properly jumped,
resulting in an early STOP (because the argument is 0).
2016-12-14 16:27:38 -05:00
niravthakkar
49182c4d2e
Added test for RRD and RRF-e
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Also have modified the function which can handle 3 arguments now
2016-12-14 19:14:10 +05:30
niravthakkar
d63ff89c54
Added support for RRD addressing mode
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We may not require RRD mode but, Added to check working of RRF-e.
2016-12-14 19:07:05 +05:30
niravthakkar
df7c3245e0
Minor Fix, correct the parameter used
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Instead of params[2] , params[1] was used, corrected it.
2016-12-14 17:45:32 +05:30
niravthakkar
52368ac005
Minor cleanup
2016-12-14 14:47:15 +05:30
niravthakkar
ccd2614902
Added support for RIE-e, RSI, RXF, SI instructions
2016-12-14 14:18:07 +05:30
niravthakkar
f01f459573
Added support for RIL-c and RX-b instructions
2016-12-14 13:51:58 +05:30
niravthakkar
a8244c02ec
Added support for RI-b and RI-c mode instructions
2016-12-14 13:41:55 +05:30
niravthakkar
4641b9a42d
Added C support for I mode instructions
2016-12-14 13:30:49 +05:30
niravthakkar
cdb31062b7
Added the action part for I mode
2016-12-14 13:24:44 +05:30
niravthakkar
52ab0596da
Added support for I mode instructions
2016-12-14 13:16:44 +05:30
niravthakkar
bc490013a3
Adding S mode instructions support
2016-12-14 13:08:32 +05:30
niravthakkar
45669fecef
Added RRF-b mode support
2016-12-14 12:34:11 +05:30
niravthakkar
2f96ca3d91
Adding support for RXE mode instructions
2016-12-14 12:29:46 +05:30
niravthakkar
fc5874c951
Added RRF-e support
2016-12-14 12:22:08 +05:30
