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164 Commits

Author SHA1 Message Date
niravthakkar
4c7e494e0a Added support for Immediate addressing mode 
Adding support for Immediate add mode, need to check how 32 bits is returned, currently followed the displacement method.
 2016-12-02 12:55:43 +05:30
Michael Munday
1b7ded5474 Add support for RS-a and RSY-a instructions like stm and stmg. 2016-12-01 19:45:06 -05:00
Michael Munday
6ae327df75 Add support for RXY instructions (20-bit displacements). 2016-12-01 19:26:30 -05:00
Michael Munday
77f283c328 Allow symbols to be used for 12-bit displacements. 
The parse_mem_bx function now returns a function to call to add an
action to the action list to handle the evaluation of the
displacement. This allows us to delay adding said action until
after we have emitted the actions for the instruction encodings
themselves.

Code like this should now work:

int x = 24
| st r1, x(sp)
 2016-12-01 17:09:45 -05:00
Michael Munday
c71a6189bb Fix indentation. 
I miss gofmt.
 2016-12-01 14:43:23 -05:00
niravthakkar
dd6448ff1e Changed the templates based on no of arguments 
Have changed the templates based on number of parameters passed, mainly the memory and immediate ones are modified.
 2016-12-01 15:15:06 +05:30
Michael Munday
575c907544 Minor cleanup of regular expressions. 2016-11-30 17:07:17 -05:00
Michael Munday
a34bcf9ef4 Add initial support for D(B,X) memory operands (12-bit only). 
Most RX instructions don't specify the correct number of operands
so this won't work on many yet. It also won't yet emit an action
if D is a variable rather than a constant.
 2016-11-30 16:05:36 -05:00
Michael Munday
cf225d27cc Fix C code in header file and handle br template. 
This means that code like this can now be generated on s390x:

| ar r2, r3
| br r14

Still need to add support for immediates, memory, labels, other
instructions and so on.
 2016-11-30 14:11:01 -05:00
Michael Munday
000b1a84f0 Breakup instructions and action list into halfword chunks. 
This should allow us to encode the instructions relatively naturally
and efficiently. For now I've escaped halfwords with a value <=
the maximum action. This means that 0 is escaped which probably
isn't ideal, so we may want to revisit that decision at some point.
 2016-11-29 18:06:59 -05:00
Michael Munday
d97dea2e3f Add a description of how immediate actions should be encoded. 
Also sets the action list type to unsigned short (uint16_t) which
I think is the most appropriate type for s390x (x86 uses uint8_t
and other platforms use uint32_t).
 2016-11-29 16:29:42 -05:00
Michael Munday
36479af87a Add stubs for parsing memory operands and delete unwanted code. 
Each memory operand will be a single parameter so we also need
to update the instruction encoding nargs field.
 2016-11-29 15:24:11 -05:00
Michael Munday
89ca41cca5 Add sp -> r15 mapping and don't special case or_2 
It's convenient for sp to be a pseudonym for r15 (the stack pointer).
'or_2' doesn't need to be special cased ('or' did because it is a
keyword).
 2016-11-29 13:59:37 -05:00
Michael Munday
0e3241180f Various cleanup of dasm_s390x.lua 
- Fix syntax errors
 - Fix whitespace (use two-space indentation to match surrounding code)
 2016-11-29 13:45:59 -05:00
niravthakkar
7a49be07be Added the required character for encoding 
I have added the number depending on the number of operands, pls check for the ones which access memory.
Also For base register and displacement, should I assume that it will be passed in the same order as it is expected, since I dont have any means to see the output, I am confused a bit for those add modes.
Since we decided to test RR first, thats in progress, but would like to add others as well.
 2016-11-29 19:00:28 +05:30
niravthakkar
538a4afee2 Updated size of the instruction word 
We can discuss if we need to keep it 6 bytes or 8 bytes long, Not clear enough to me as well
 2016-11-28 15:29:58 +05:30
niravthakkar
203006579f Removed the extra check in parse_reg 
The extra check for register is currently ignored, and trying to see what value does the encode function return. Its still to be worked out, how this value is used later, after decoding.
 2016-11-28 13:32:30 +05:30
Michael Munday
cac5d4f2fb Add extended mnemonics for branches. 2016-11-25 16:38:32 -05:00
niravthakkar
9b01b4dc6f Added s390x instructions with their encoding 2016-11-25 19:44:04 +05:30
niravthakkar
dcb977d1db Changed the encoding for add,and,branch instructions 2016-11-16 14:44:12 +05:30
niravthakkar
9583ba36de Created s390x header file 
Currently copy of ppc.h, which is same as arm64.h, and added the architecture definition
 2016-11-10 19:00:51 +05:30
niravthakkar
f1f03ec44b Copy of dasm_arm64.lua file, with few changes 
Have changed few sections of file, other part is common across architectures
 2016-11-10 19:00:41 +05:30
Mike Pall
e3c4c9af0f DynASM/MIPS: Add missing MIPS64 instructions. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
Sponsored by Cisco Systems, Inc.
 2016-05-28 05:09:24 +02:00
Mike Pall
75d046dbdd DynASM/x86: Add ADX instructions. 
Thanks to Peter Cawley.
 2016-03-06 12:25:03 +01:00
Mike Pall
f4231949b5 Merge branch 'master' into v2.1 2016-03-03 12:11:37 +01:00
Mike Pall
db1b399af1 Bump copyright date to 2016. 2016-03-03 12:02:22 +01:00
Mike Pall
22e7b00ddb DynASM/x64: Fix for full VREG support. 
Thanks to Peter Cawley.
 2015-12-28 17:06:48 +01:00
Mike Pall
cfae3846f8 DynASM/x86: Add AVX AES instructions. 
Contributed by Peter Cawley.
 2015-12-28 16:40:39 +01:00
Mike Pall
a687a60eaa DynASM/x64: Add full VREG support. 
Contributed by Peter Cawley.
 2015-12-28 13:44:13 +01:00
Mike Pall
0aa337a41c Merge branch 'master' into v2.1 2015-11-04 14:09:59 +01:00
Mike Pall
367cba29ea DynASM/x86: Add rdpmc instruction. 
Thanks to Cosmin Apreutesei.
 2015-11-04 14:04:19 +01:00
Mike Pall
4c08158be4 Whitespace. 2015-10-24 18:53:37 +02:00
Mike Pall
d62dc01984 DynASM: Bump version to 1.4. 
Thanks to Peter Cawley.
 2015-10-24 18:46:45 +02:00
Mike Pall
8a13c9cebf DynASM/x86: Add AVX and AVX2 opcodes. 
Thanks to Peter Cawley.
 2015-10-24 18:43:47 +02:00
Mike Pall
7e22082480 DynASM/x86: Add AES-NI opcodes. 
Thanks to Peter Cawley.
 2015-10-24 18:18:52 +02:00
Mike Pall
e54ca424b5 Merge branch 'master' into v2.1 2015-10-24 18:18:07 +02:00
Mike Pall
7579b161af DynASM/x86: Restrict shld/shrd to operands with same width. 
Thanks to Peter Cawley.
 2015-10-24 18:15:44 +02:00
Mike Pall
9dc785e0af DynASM/x86: Fix some SSE instruction templates. 
Thanks to Peter Cawley.
 2015-10-24 18:12:40 +02:00
Mike Pall
1c968d5b63 DynASM/PPC: Add sub/shift/rotate/clear instruction aliases. 2015-04-12 03:46:16 +02:00
Mike Pall
b2a5cc8233 DynASM/PPC: Add support for parameterized shifts/masks. 2015-04-12 01:25:14 +02:00
Mike Pall
3e1703895a DynASM/PPC: Add missing PPC64 instructions and various extensions. 
Contributed by Caio Souza Oliveira.
 2015-01-14 21:40:24 +01:00
Mike Pall
1b1bd08d3c DynASM/ARM64: Fix checks for scaled immediates. 2015-01-07 13:17:11 +01:00
Mike Pall
0a5045c34e Merge branch 'master' into v2.1 2015-01-06 00:12:45 +01:00
Mike Pall
86913b9bbf Bump copyright date to 2015. 2015-01-05 23:59:31 +01:00
Mike Pall
a13dfd66c3 DynASM/ARM64: Various fixes. 2014-12-27 06:13:48 +01:00
Mike Pall
7a76d435da Merge branch 'master' into v2.1 2014-12-27 06:11:14 +01:00
Mike Pall
db7cb5ab0e DynASM/ARM: Fix rollback for variant templates. 2014-12-27 06:08:36 +01:00
Mike Pall
f49c61a277 DynASM/ARM64: Initial commit of ARM64 module. 2014-12-03 14:12:02 +01:00
Mike Pall
3f2e4ec699 DynASM/ARM: Fix description shown for multi-element templates. 2014-12-03 14:09:17 +01:00
Mike Pall
cb886b5817 DynASM/x86: Add fldenv, f[n]stenv, fxsave, fxrstor opcodes. 
Thanks to Cosmin Apreutesei.
 2014-09-22 13:44:28 +02:00
Mike Pall
ae7d4d5ad6 DynASM/x86: Add shld/shrd opcodes. 
Thanks to Peter Cawley.
 2014-09-21 18:03:47 +02:00
Mike Pall
80efb07750 DynASM: Emit version check after .arch directive. 2014-03-06 17:54:48 +01:00
Mike Pall
ef59e54820 Bump copyright date to 2014. 2014-01-16 23:10:16 +01:00
Mike Pall
1f7b326217 DynASM: Emit #line <n> <file> instead of #<n> <file>. 2013-09-12 12:46:28 +02:00
Mike Pall
ec96d8b494 DynASM/x64: Add VREG support to mov64. 
Thanks to Peter Cawley.
 2013-07-18 08:51:32 +02:00
Mike Pall
b2a13ddd74 DynASM/x86: Add lock prefix. 2013-06-24 12:20:25 +02:00
Mike Pall
d147eedac9 DynASM: Improve validation of local backwards relocations. 2013-03-17 14:20:40 +01:00
Mike Pall
4a44c4ff69 Bump copyright date to 2013. 2013-02-11 12:54:48 +01:00
Mike Pall
894d2d6ef4 DynASM/ARM: Fix conditional VFP instruction encoding. 2012-10-15 16:52:18 +02:00
Mike Pall
2d58872cb5 DynASM/ARM: Add VFP instructions. 2012-07-29 12:16:33 +02:00
Mike Pall
c00ffcb870 Change DynASM bit operations to use Lua BitOp. 2012-07-08 16:27:18 +02:00
Mike Pall
6b605bd455 DynASM/PPC: Add missing 64 bit rotates and mtocrf/mfocrf. 2012-06-12 16:47:25 +02:00
Mike Pall
6c8aaef2bb DynASM: Compatibility with minilua. 2012-06-09 14:42:03 +02:00
Mike Pall
6c05739684 DynASM: Lua 5.2 compatibility fixes. 2012-02-17 11:40:18 +01:00
Mike Pall
10ef109eef Bump copyright date to 2012. 2012-01-23 22:42:42 +01:00
Mike Pall
b9651b4ba2 MIPS: Add missing opcodes to the DynASM MIPS module plus minor fixes. 
Allow single dot as macro name.
 2012-01-23 19:06:58 +01:00
Mike Pall
ba4917b71b MIPS: Add DynASM MIPS module and encoding engine. 2011-12-16 21:33:40 +01:00
Mike Pall
9df9c7ef73 PPC: Fix externally provided relocation offsets in DynASM. 2011-10-25 01:18:59 +02:00
Mike Pall
e2b89de92d PPC: Add y-bit variants of conditional branches to DynASM. 2011-09-05 18:26:08 +02:00
Mike Pall
ec1b70ae35 PPC: Add PPC disassembler. 2011-08-18 19:41:27 +02:00
Mike Pall
b500b50edc Clarify name of MIT license. 2011-08-14 21:18:58 +02:00
Mike Pall
5385809d30 PPC: Add mtcrf instruction to DynASM. 2011-08-10 21:50:11 +02:00
Mike Pall
fe1f9137a9 PPC: Fix range check for scaled immediates in DynASM. 2011-07-02 00:43:19 +02:00
Mike Pall
f0a7293e58 ARM: Remove redundant parse_gpr() in DynASM. 2011-05-16 02:39:26 +02:00
Mike Pall
cfdc356ebe RELEASE LuaJIT-2.0.0-beta7 2011-05-05 16:31:13 +02:00
Mike Pall
7ff8409797 DynASM: x86/x64: Fix vreg in opcode. x64: Fix imm "I" after abs addr. 2011-04-28 12:54:46 +02:00
Mike Pall
161bc379f0 ARM: Add GPR variants for shift aliases to DynASM. 2011-04-10 16:50:04 +02:00
Mike Pall
3f8fed5358 ARM: Add pc-relative loads to DynASM. 2011-04-08 02:44:21 +02:00
Mike Pall
33bab1f76c ARM: Don't conditionalize non-opcodes in DynASM. 2011-04-04 01:39:19 +02:00
Mike Pall
2138df2662 ARM: Fix escaping of opcodes in DynASM. 2011-04-03 20:49:51 +02:00
Mike Pall
492efb7e7e Clean up DynASM glue macros. Thanks to Josh Haberman. 2011-03-28 15:06:30 +02:00
Mike Pall
b6ed984843 ARM: Add support for ARM relocations to buildvm. 2011-03-26 18:40:11 +01:00
Mike Pall
156bf15783 ARM: Add DynASM ARM module and encoding engine. 2011-03-23 01:25:14 +01:00
Mike Pall
06f99fc3df Bump copyright date to 2011. 2011-01-09 17:12:53 +01:00
Mike Pall
559545eb6d Whitespace. 2010-12-05 01:14:18 +01:00
Mike Pall
a36287b218 PPC: Add better diagnostics to DynASM for reg/imm mismatches. 2010-09-14 00:00:31 +02:00
Mike Pall
cd6a45760a PPC: Teach DynASM to reject r0 for some operands. 2010-09-13 21:11:51 +02:00
Mike Pall
b72ae54dc0 Fix broken MSVC build. 2010-09-12 01:33:32 +02:00
Mike Pall
7313a0821d PPC: Add missing PowerPC subtract mnemonics. 2010-08-29 12:58:22 +02:00
Mike Pall
9c16a9f705 PPC: Amend DynASM PowerPC conditional branch instructions. 2010-08-28 20:05:57 +02:00
Mike Pall
1b57266668 PPC: Add SPE instructions to DynASM PowerPC module. 2010-08-27 01:43:32 +02:00
Mike Pall
4aa8757aac PPC: Add DynASM PowerPC encoding engine. 2010-08-26 17:27:17 +02:00
Mike Pall
4f47d31fef PPC: Add DynASM PowerPC module. Standard instructions only. 2010-08-26 02:09:15 +02:00
Mike Pall
0d6f6f3fa0 Clean up some more DynASM target dependencies. 2010-08-08 18:03:20 +02:00
Mike Pall
309d8f5aab Cleanup library function caching in dasm_x86.lua. 2010-08-03 22:32:43 +02:00
Mike Pall
4d9be5b8f8 Bump all copyright dates to 2010. 2010-01-09 14:28:11 +01:00
Mike Pall
9df01f96b9 Allow @ in DynASM globals. 2010-01-05 22:07:54 +01:00
Mike Pall
da65e0dfed Fix DynASM x64 encoding for qword-only instructions. 2009-12-28 21:00:03 +01:00
Mike Pall
e5438daffe Ignore lea operand size in DynASM x86/x64. 2009-12-27 18:25:01 +01:00
Mike Pall
64a4528cac Fix memory operand sizes for some SSE ops in DynASM. 2009-12-21 16:41:03 +01:00