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51 Commits

Author SHA1 Message Date
Mike Pall
7ff8f26eb8 ARM64: Fix register allocation for IR_*LOAD. 
Thanks to Peter Cawley. #1062
 2023-08-29 22:35:10 +02:00
Mike Pall
83954100db FFI/ARM64/OSX: Handle non-standard OSX C calling conventions. 
Contributed by Peter Cawley. #205
 2023-08-29 02:21:51 +02:00
Mike Pall
7cc53f0b85 ARM64: Prevent STP fusion for conditional code emitted by TBAR. 
Thanks to Peter Cawley. #1057
 2023-08-28 22:39:35 +02:00
Mike Pall
ef587afb2c Merge branch 'master' into v2.1 2023-08-20 21:33:37 +02:00
Mike Pall
27af72e66f ARM64: Add support for ARM64e pointer authentication codes (PAC). 
Contributed by Peter Cawley. #559
 2023-08-12 22:25:40 +02:00
Mike Pall
93ce12ee15 ARM64: Fix assembly of HREFK (again). 
Thanks to Peter Cawley. #1026
 2023-08-12 14:52:48 +02:00
Mike Pall
8635cbabf3 Merge branch 'master' into v2.1 2023-07-12 22:34:46 +02:00
Mike Pall
8fbd576fb9 ARM64: Fix assembly of HREFK. 
Reported by caohongqing. #1026
Fix contributed by Peter Cawley.
 2023-07-09 21:15:01 +02:00
Mike Pall
de2e1ca9d3 Disable FMA by default. Use -Ofma or jit.opt.start("+fma") to enable. 
See the discussion in #918 for the rationale.
 2022-12-07 18:38:22 +01:00
Mike Pall
564147f518 ARM64: Fix code generation for IR_SLOAD with typecheck + conversion. 
Reported by memcorrupt.
 2022-12-01 12:03:09 +01:00
Mike Pall
6c4826f12c ARM64: Fix IR_SLOAD assembly. 
Reported by Gate88.
 2022-10-04 12:04:17 +02:00
Mike Pall
1cdff194cf Add missing check for LJ_KEYINDEX in ITERN recording. 
Reported by dragonorloong. Analyzed by vfprintf. #827
 2022-04-02 21:27:43 +02:00
Mike Pall
7306ba78d6 Merge branch 'master' into v2.1 2022-01-15 19:42:30 +01:00
Mike Pall
e4b4d94514 ARM64: Fix IR_HREF code generation. 2021-10-02 17:49:50 +02:00
Mike Pall
bb0f241015 Compile table traversals: next(), pairs(), BC_ISNEXT/BC_ITERN. 
Sponsored by OpenResty Inc.
 2021-09-19 17:49:25 +02:00
Mike Pall
986bb406ad Use IR_HIOP for generalized two-register returns. 
Sponsored by OpenResty Inc.
 2021-09-19 17:47:11 +02:00
Mike Pall
9211f0b03b Refactor IR_VLOAD to take an offset. 2021-09-19 17:18:16 +02:00
Mike Pall
f2d333c1ac MIPS: Fix trace linking. 2021-09-19 16:09:48 +02:00
Mike Pall
02bcbea8b0 String buffers, part 3c: Add IRBUFHDR_WRITE mode. 
Sponsored by fmad.io.
 2021-07-19 16:46:27 +02:00
Mike Pall
6df650fe3f String buffers, part 3a: Add IR_TMPREF for passing TValues to helpers. 
Sponsored by fmad.io.
 2021-07-19 16:23:12 +02:00
Mike Pall
71db0cf043 Add IRCONV_NONE for pass-through INT to I64/U64 type change. 2021-07-19 16:11:39 +02:00
Mike Pall
69138082a3 ARM64: More improvements to the generation of immediates. 2021-06-03 03:21:56 +02:00
Mike Pall
1e66d0f9e6 Merge branch 'master' into v2.1 2021-01-02 21:56:07 +01:00
Mike Pall
e67e2040be ARM64: Followup fix for exit branch patching. 2020-09-28 18:17:58 +02:00
Mike Pall
2e55a42c07 Merge branch 'master' into v2.1 2020-09-27 17:20:37 +02:00
Mike Pall
ff34b48ddd Redesign and harden string interning. 
Up to 40% faster on hash-intensive benchmarks.
With some ideas from Sokolov Yura.
 2020-06-23 03:06:45 +02:00
Mike Pall
8ae5170cdc Improve assertions. 2020-06-15 02:52:00 +02:00
Mike Pall
b2307c8ad8 Remove pow() splitting and cleanup backends. 2020-05-23 21:33:01 +02:00
Mike Pall
5655be4546 Cleanup math function compilation and fix inconsistencies. 2020-05-22 04:53:35 +02:00
Mike Pall
03208c8162 Fix math.min()/math.max() inconsistencies. 2020-05-22 03:10:30 +02:00
Mike Pall
5bf0da3d7c ARM64: Fix {AHUV}LOAD specialized to nil/false/true. 
Reported by caohongqing.
 2020-05-18 22:24:53 +02:00
Mike Pall
87b111f0fe Merge branch 'master' into v2.1 2020-01-20 23:34:21 +01:00
Mike Pall
b33e3f2d44 ARM64: Avoid side-effects of constant rematerialization. 
Thanks to Patrick Galizia.
 2019-02-04 23:04:48 +01:00
Mike Pall
9da0653509 ARM64: Fix exit stub patching. 
Contributed by Javier Guerra Giraldez.
 2018-06-24 14:08:59 +02:00
Mike Pall
06cd9fce7d ARM64: Fix assembly of HREFK. 
Reported by Jason Teplitz.
 2017-11-08 12:53:48 +01:00
Mike Pall
3143b21894 ARM64: Add big-endian support. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
Sponsored by Cisco Systems, Inc.
 2017-03-30 11:30:01 +02:00
Mike Pall
0cf78854a9 ARM64: Fix XLOAD/XSTORE with FP operand. 
Thanks to Stefan Pejic.
 2017-03-20 23:49:57 +01:00
Mike Pall
0a46ef1ac6 ARM64: Cleanup and de-cargo-cult TValue store generation. 2017-02-20 02:41:35 +01:00
Mike Pall
5aa0201374 ARM64: Fix AREF/HREF/UREF fusion. 
Thanks to Zhongwei Yao.
 2017-02-16 20:41:46 +01:00
Mike Pall
71ff7ef8a7 Merge branch 'master' into v2.1 2017-01-17 12:41:05 +01:00
Mike Pall
ebec2530be ARM64: Fuse BOR/BXOR and BNOT into ORN/EON. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
 2016-12-15 22:47:40 +01:00
Mike Pall
4ccd876a65 ARM64: Use the correct FUSE check. 
Oops, my bad.
 2016-12-09 18:24:48 +01:00
Mike Pall
44b99ff14d ARM64: Fuse BOR(BSHL, BSHR) into EXTR/ROR. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
 2016-12-09 18:16:12 +01:00
Mike Pall
986854cbb2 ARM64: Fix code generation for S19 offsets. 
Contributed by Zhongwei Yao.
 2016-12-08 05:53:36 +01:00
Mike Pall
3975b6c9f4 ARM64: Fuse various BAND/BSHL/BSHR/BSAR combinations. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
 2016-12-08 04:09:29 +01:00
Mike Pall
2772cbc36e ARM64: Fuse FP multiply-add/sub. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
 2016-12-08 01:38:09 +01:00
Mike Pall
bfeb1167cd ARM64: Fuse XLOAD/XSTORE with STRREF/ADD/BSHL/CONV. 2016-12-07 18:40:31 +01:00
Mike Pall
2ac2cd4699 ARM64: Reorganize operand extension definitions. 2016-12-07 18:38:32 +01:00
Mike Pall
3ad2bbf586 ARM64: Make use of tbz/tbnz and cbz/cbnz. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
 2016-11-29 19:30:40 +01:00
Mike Pall
81259898ea ARM64: Emit more efficient trace exits. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
 2016-11-24 18:56:19 +01:00