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118 Commits

Author SHA1 Message Date
gns
bedd0cf1e1 riscv(support,linux): use HWPROBE for ISE detection 
Current SIGILL handler appears to have weird issues with libluajit on
some platform. Considering 6.6 kernel is becoming more common, switch
to HWPROBE for better compatibility.
 2025-01-23 14:19:16 +08:00
gns
e1ce400d1f riscv(support): add extension detection 2025-01-23 14:17:20 +08:00
Mike Pall
8358eb0cce Merge branch 'master' into v2.1 2025-01-13 16:15:19 +01:00
Mike Pall
e8236561d4 Bump copyright date. 2025-01-13 15:59:10 +01:00
Mike Pall
80c1c65bce Typo. 2024-05-25 16:25:35 +02:00
Mike Pall
356231edaf Merge branch 'master' into v2.1 2023-08-29 22:30:57 +02:00
Mike Pall
c6ee7e19d1 Update external MSDN URL in code. 
Thanks to Kyle Marshall. #1060
 2023-08-29 22:27:38 +02:00
Mike Pall
ef587afb2c Merge branch 'master' into v2.1 2023-08-20 21:33:37 +02:00
Mike Pall
158a284cc9 Bump copyright date. 2023-08-20 21:25:30 +02:00
Mike Pall
27af72e66f ARM64: Add support for ARM64e pointer authentication codes (PAC). 
Contributed by Peter Cawley. #559
 2023-08-12 22:25:40 +02:00
Mike Pall
de2e1ca9d3 Disable FMA by default. Use -Ofma or jit.opt.start("+fma") to enable. 
See the discussion in #918 for the rationale.
 2022-12-07 18:38:22 +01:00
Mike Pall
96157d360d Avoid zero-sized arrays in jit_State. 2022-06-08 11:26:50 +02:00
Mike Pall
b32e94856b Don't use jit_State during build with JIT disabled. 2022-06-08 11:20:28 +02:00
Mike Pall
7306ba78d6 Merge branch 'master' into v2.1 2022-01-15 19:42:30 +01:00
Mike Pall
c4dfb625ba Bump copyright date. 2022-01-15 19:30:54 +01:00
Mike Pall
bb0f241015 Compile table traversals: next(), pairs(), BC_ISNEXT/BC_ITERN. 
Sponsored by OpenResty Inc.
 2021-09-19 17:49:25 +02:00
Mike Pall
a32aeadc68 Handle on-trace OOM errors from helper functions. 2021-03-23 00:39:50 +01:00
Mike Pall
1e66d0f9e6 Merge branch 'master' into v2.1 2021-01-02 21:56:07 +01:00
Mike Pall
f47c864b01 Bump copyright date. 2021-01-02 21:49:41 +01:00
Mike Pall
10ddae75af Merge branch 'master' into v2.1 2020-08-05 15:26:59 +02:00
Mike Pall
2211f6f960 ARM: Ensure relative GG_State element alignment differently. 
Thanks to jojo59516 and dwing4g.
 2020-08-05 15:21:00 +02:00
Mike Pall
a44f53acf5 Use a securely seeded global PRNG for the VM. 
It's not 2005 anymore.
 2020-06-15 12:21:05 +02:00
Mike Pall
8ae5170cdc Improve assertions. 2020-06-15 02:52:00 +02:00
Mike Pall
0eddcbead2 Cleanup CPU detection and tuning for old CPUs. 2020-05-20 20:42:04 +02:00
Mike Pall
87b111f0fe Merge branch 'master' into v2.1 2020-01-20 23:34:21 +01:00
Mike Pall
38a5ed4b43 Bump copyright date. 2020-01-20 23:26:51 +01:00
Mike Pall
94d0b53004 MIPS: Add MIPS64 R6 port. 
Contributed by Hua Zhang, YunQiang Su from Wave Computing,
and Radovan Birdic from RT-RK.
Sponsored by Wave Computing.
 2020-01-20 22:15:45 +01:00
Mike Pall
749e99ce2a Merge branch 'master' into v2.1 2019-01-10 12:24:17 +01:00
Mike Pall
380e4409a7 Fix overflow of snapshot map offset. 
Thanks to Yichun Zhang.
 2019-01-10 12:19:30 +01:00
Mike Pall
a057a07ab7 MIPS64: Add soft-float support to JIT compiler backend. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
Sponsored by Cisco Systems, Inc.
 2017-06-07 23:56:54 +02:00
Mike Pall
0e4a551809 Merge branch 'master' into v2.1 2017-06-07 19:39:41 +02:00
Mike Pall
c7c3c4da43 MIPS: Fix handling of spare long-range jump slots. 
Contributed by Djordje Kovacevic and Stefan Pejic.
 2017-06-07 19:36:46 +02:00
Mike Pall
a25c0b99b8 MIPS64, part 2: Add MIPS64 hard-float JIT compiler backend. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
Sponsored by Cisco Systems, Inc.
 2017-02-20 03:43:10 +01:00
Mike Pall
71ff7ef8a7 Merge branch 'master' into v2.1 2017-01-17 12:41:05 +01:00
Mike Pall
b93a1dd0c8 Bump copyright date to 2017. 2017-01-17 12:35:03 +01:00
Mike Pall
d9986fbadb MIPS64, part 1: Add MIPS64 support to interpreter. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
Sponsored by Cisco Systems, Inc.
 2016-05-28 05:10:55 +02:00
Mike Pall
6c8258d74b LJ_FR2: Add support for trace recording and snapshots. 
Contributed by Peter Cawley.
 2016-05-23 01:49:00 +02:00
Mike Pall
9e99ccc360 Strip out old infrastructure for 64 bit constants. 
Contributed by Peter Cawley.
 2016-05-23 00:27:51 +02:00
Mike Pall
7fb75ccc4c Embed 64 bit constants directly in the IR, using two slots. 
Contributed by Peter Cawley.
 2016-05-23 00:25:29 +02:00
Mike Pall
3152ed98ea Simplify GCtrace * reference embedding for trace stitching. 
This is now possible due to the immovable IR.
Contributed by Peter Cawley.
 2016-05-22 23:40:37 +02:00
Mike Pall
a657fa0186 Make the IR immovable after assembly. 
This allows embedding pointers to IR constants in the machine code.
Contributed by Peter Cawley.
 2016-05-22 23:25:28 +02:00
Mike Pall
cfa188f134 Move common 32/64 bit in-memory FP constants to jit_State. 
Prerequisite for immovable IR.
Contributed by Peter Cawley.
 2016-05-21 00:02:45 +02:00
Mike Pall
6801e7165c x86: Detect BMI2 instruction support. 2016-03-28 23:04:33 +02:00
Mike Pall
f4231949b5 Merge branch 'master' into v2.1 2016-03-03 12:11:37 +01:00
Mike Pall
db1b399af1 Bump copyright date to 2016. 2016-03-03 12:02:22 +01:00
Mike Pall
a3a6866d4c Re-enable trace stitching. 
Thanks to Vyacheslav Egorov.
 2015-08-29 23:24:26 +02:00
Mike Pall
fe565222a1 Disable table allocation bump optimization (for now). 2015-06-13 00:42:38 +02:00
Mike Pall
60fb3fe2b2 Fix table allocation bump optimization. 2015-05-21 16:38:31 +02:00
Mike Pall
b82fc3ddc0 Bump table allocations retroactively if they grow later on. 2015-05-19 01:59:29 +02:00
Mike Pall
0a5045c34e Merge branch 'master' into v2.1 2015-01-06 00:12:45 +01:00