Mike Pall
|
44b99ff14d
|
ARM64: Fuse BOR(BSHL, BSHR) into EXTR/ROR.
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
|
2016-12-09 18:16:12 +01:00 |
|
Mike Pall
|
986854cbb2
|
ARM64: Fix code generation for S19 offsets.
Contributed by Zhongwei Yao.
|
2016-12-08 05:53:36 +01:00 |
|
Mike Pall
|
3975b6c9f4
|
ARM64: Fuse various BAND/BSHL/BSHR/BSAR combinations.
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
|
2016-12-08 04:09:29 +01:00 |
|
Mike Pall
|
2772cbc36e
|
ARM64: Fuse FP multiply-add/sub.
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
|
2016-12-08 01:38:09 +01:00 |
|
Mike Pall
|
bfeb1167cd
|
ARM64: Fuse XLOAD/XSTORE with STRREF/ADD/BSHL/CONV.
|
2016-12-07 18:40:31 +01:00 |
|
Mike Pall
|
2ac2cd4699
|
ARM64: Reorganize operand extension definitions.
|
2016-12-07 18:38:32 +01:00 |
|
Mike Pall
|
3ad2bbf586
|
ARM64: Make use of tbz/tbnz and cbz/cbnz.
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
|
2016-11-29 19:30:40 +01:00 |
|
Mike Pall
|
81259898ea
|
ARM64: Emit more efficient trace exits.
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
|
2016-11-24 18:56:19 +01:00 |
|
Mike Pall
|
04b60707d7
|
ARM64: Add JIT compiler backend.
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
Sponsored by Cisco Systems, Inc.
|
2016-11-20 22:18:14 +01:00 |
|