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21 Commits

Author SHA1 Message Date
Mike Pall
8dc3cd6c84 DynASM: Bump version to 1.5.0. 2021-05-02 22:29:01 +02:00
Mike Pall
1e66d0f9e6 Merge branch 'master' into v2.1 2021-01-02 21:56:07 +01:00
Mike Pall
f47c864b01 Bump copyright date. 2021-01-02 21:49:41 +01:00
Mike Pall
87b111f0fe Merge branch 'master' into v2.1 2020-01-20 23:34:21 +01:00
Mike Pall
38a5ed4b43 Bump copyright date. 2020-01-20 23:26:51 +01:00
Mike Pall
94d0b53004 MIPS: Add MIPS64 R6 port. 
Contributed by Hua Zhang, YunQiang Su from Wave Computing,
and Radovan Birdic from RT-RK.
Sponsored by Wave Computing.
 2020-01-20 22:15:45 +01:00
Mike Pall
617f532542 Merge branch 'master' into v2.1 2019-01-10 12:34:20 +01:00
Mike Pall
5c911998a3 DynASM/MIPS: Fix shadowed variable. 
Cleanup only, bug cannot trigger.
Thanks to Domingo Alvarez Duarte.
 2019-01-10 12:32:08 +01:00
Mike Pall
71ff7ef8a7 Merge branch 'master' into v2.1 2017-01-17 12:41:05 +01:00
Mike Pall
b93a1dd0c8 Bump copyright date to 2017. 2017-01-17 12:35:03 +01:00
Mike Pall
e3c4c9af0f DynASM/MIPS: Add missing MIPS64 instructions. 
Contributed by Djordje Kovacevic and Stefan Pejic from RT-RK.com.
Sponsored by Cisco Systems, Inc.
 2016-05-28 05:09:24 +02:00
Mike Pall
f4231949b5 Merge branch 'master' into v2.1 2016-03-03 12:11:37 +01:00
Mike Pall
db1b399af1 Bump copyright date to 2016. 2016-03-03 12:02:22 +01:00
Mike Pall
d62dc01984 DynASM: Bump version to 1.4. 
Thanks to Peter Cawley.
 2015-10-24 18:46:45 +02:00
Mike Pall
86913b9bbf Bump copyright date to 2015. 2015-01-05 23:59:31 +01:00
Mike Pall
ef59e54820 Bump copyright date to 2014. 2014-01-16 23:10:16 +01:00
Mike Pall
4a44c4ff69 Bump copyright date to 2013. 2013-02-11 12:54:48 +01:00
Mike Pall
c00ffcb870 Change DynASM bit operations to use Lua BitOp. 2012-07-08 16:27:18 +02:00
Mike Pall
10ef109eef Bump copyright date to 2012. 2012-01-23 22:42:42 +01:00
Mike Pall
b9651b4ba2 MIPS: Add missing opcodes to the DynASM MIPS module plus minor fixes. 
Allow single dot as macro name.
 2012-01-23 19:06:58 +01:00
Mike Pall
ba4917b71b MIPS: Add DynASM MIPS module and encoding engine. 2011-12-16 21:33:40 +01:00