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https://github.com/LuaJIT/LuaJIT.git
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LoongArch64: Add LoongArch instruction emitter
Co-developed-by: Qiqi Huang <huangqiqi@loongson.cn>
This commit is contained in:
Xiaolin Zhao
parent
07c315164f
commit
e8eb730bb6
306
src/lj_emit_loongarch64.h
Normal file
306
src/lj_emit_loongarch64.h
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@ -0,0 +1,306 @@
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/*
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** LoongArch instruction emitter.
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** Copyright (C) 2005-2022 Mike Pall. See Copyright Notice in luajit.h
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*/
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static intptr_t get_k64val(ASMState *as, IRRef ref)
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{
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IRIns *ir = IR(ref);
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if (ir->o == IR_KINT64) {
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return (intptr_t)ir_kint64(ir)->u64;
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} else if (ir->o == IR_KGC) {
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return (intptr_t)ir_kgc(ir);
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} else if (ir->o == IR_KPTR || ir->o == IR_KKPTR) {
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return (intptr_t)ir_kptr(ir);
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} else {
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lj_assertA(ir->o == IR_KINT || ir->o == IR_KNULL,
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"bad 64 bit const IR op %d", ir->o);
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return ir->i; /* Sign-extended. */
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}
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}
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#define get_kval(as, ref) get_k64val(as, ref)
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/* -- Emit basic instructions --------------------------------------------- */
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static void emit_djk(ASMState *as, LOONGIns loongi, Reg rd, Reg rj, Reg rk)
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{
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*--as->mcp = loongi | LOONGF_D(rd & 0x1f) | LOONGF_J(rj & 0x1f) | LOONGF_K(rk & 0x1f);
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}
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#define emit_dj(as, loongi, rd, rj) emit_djk(as, loongi, rd, rj, 0)
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static void emit_di(ASMState *as, LOONGIns loongi, Reg rd, int32_t i)
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{
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*--as->mcp = loongi | LOONGF_D(rd & 0x1f) | LOONGF_I20(i & 0xfffff);
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}
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static void emit_dji(ASMState *as, LOONGIns loongi, Reg rd, Reg rj, int32_t i)
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{
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*--as->mcp = loongi | LOONGF_D(rd & 0x1f) | LOONGF_J(rj & 0x1f) | LOONGF_I(i);
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}
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static void emit_dju(ASMState *as, LOONGIns loongi, Reg rd, Reg rj, uint32_t u)
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{
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*--as->mcp = loongi | LOONGF_D(rd & 0x1f) | LOONGF_J(rj & 0x1f) | LOONGF_I(u);
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}
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#define checki12(x) LOONGF_S_OK(x, 12)
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#define checku12(x) ((x) == ((x) & 0xfff))
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static Reg ra_allock(ASMState *as, intptr_t k, RegSet allow);
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static void ra_allockreg(ASMState *as, intptr_t k, Reg r);
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static Reg ra_scratch(ASMState *as, RegSet allow);
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static void emit_dj32i(ASMState *as, Reg rd, Reg rj, int32_t i)
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{
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if (checki12(i)) {
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*--as->mcp = LOONGI_ADDI_D | LOONGF_D(rd) | LOONGF_J(rj) | LOONGF_I(i&0xfff);
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} else {
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emit_djk(as, LOONGI_ADD_D, rd, RID_R20, rj);
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emit_dju(as, LOONGI_ORI, RID_R20, RID_R20, i&0xfff);
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emit_di(as, LOONGI_LU12I_W, RID_R20, (i>>12)&0xfffff);
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}
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}
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static void emit_d16i(ASMState *as, Reg rd, int32_t i)
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{
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emit_dji(as, LOONGI_SRAI_D, rd, rd, 16);
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emit_dji(as, LOONGI_ADDU16I_D, rd, RID_ZERO, (i&0xffff));
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}
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static void emit_djml(ASMState *as, LOONGIns loongi, Reg rd, Reg rj, uint32_t m, uint32_t l)
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{
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*--as->mcp = loongi | LOONGF_D(rd & 0x1f) | LOONGF_J(rj & 0x1f) | LOONGF_I(l & 0x3f) | LOONGF_M(m & 0x3f);
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}
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static void emit_djka(ASMState *as, LOONGIns loongi, Reg rd, Reg rj, Reg rk, Reg ra)
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{
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*--as->mcp = loongi | LOONGF_D(rd & 0x1f) | LOONGF_J(rj & 0x1f) | LOONGF_K(rk & 0x1f) | LOONGF_A(ra & 0x1f);
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}
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static void emit_b_bl(ASMState *as, LOONGIns loongi, uint32_t i)
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{
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*--as->mcp = loongi | LOONGF_I(i & 0xffff) | ((i >> 16) & 0x3ff);
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}
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/* -- Emit loads/stores --------------------------------------------------- */
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/* Prefer rematerialization of BASE/L from global_State over spills. */
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#define emit_canremat(ref) ((ref) <= REF_BASE)
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/* Load a 32 bit constant into a GPR. */
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static void emit_loadi(ASMState *as, Reg r, int32_t i)
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{
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emit_dj32i(as, r, RID_ZERO, i);
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}
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/* Load a 64 bit constant into a GPR. */
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static void emit_loadu64(ASMState *as, Reg r, uint64_t u64)
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{
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if (checki32((int64_t)u64)) {
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emit_dj32i(as, r, RID_ZERO, (int32_t)u64);
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} else {
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*--as->mcp = LOONGI_LU52I_D | LOONGF_D(r) | LOONGF_J(r) | LOONGF_I((u64>>52)&0xfff);
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*--as->mcp = LOONGI_LU32I_D | LOONGF_D(r) | LOONGF_I20((u64>>32)&0xfffff);
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*--as->mcp = LOONGI_ORI | LOONGF_D(r) | LOONGF_J(r) | LOONGF_I(u64&0xfff);
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*--as->mcp = LOONGI_LU12I_W | LOONGF_D(r) | LOONGF_I20((u64>>12)&0xfffff);
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}
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}
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#define emit_loada(as, r, addr) emit_loadu64(as, (r), u64ptr((addr)))
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/* Get/set from constant pointer. */
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static void emit_lsptr(ASMState *as, LOONGIns loongi, Reg r, void *p, RegSet allow)
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{
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intptr_t jgl = (intptr_t)(J2G(as->J));
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intptr_t i = (intptr_t)(p);
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Reg base;
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if ((uint32_t)(i-jgl) < 65536) {
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i = i-jgl-32768;
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base = RID_JGL;
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} else {
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base = ra_allock(as, i-(int16_t)i, allow);
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}
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if (checki12(i)) {
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emit_dji(as, loongi, r, base, i&0xfff);
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}
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else {
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/* ld.d->ldx.d, fld.d->fldx.d, ld.s->fldx.s */
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if (loongi == LOONGI_LD_D)
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loongi = LOONGI_LDX_D;
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else if (loongi == LOONGI_FLD_D)
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loongi = LOONGI_FLDX_D;
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else if (loongi == LOONGI_FLD_S)
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loongi = LOONGI_FLDX_S;
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emit_djk(as, loongi, r, base, RID_R20);
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/* move i to a GPR */
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emit_d16i(as, RID_R20, i); // i&0xffff
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}
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}
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/* Load 64 bit IR constant into register. */
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static void emit_loadk64(ASMState *as, Reg r, IRIns *ir)
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{
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const uint64_t *k = &ir_k64(ir)->u64;
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Reg r64 = r;
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if (rset_test(RSET_FPR, r)) {
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r64 = RID_TMP;
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emit_dj(as, LOONGI_MOVGR2FR_D, r, r64);
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}
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if ((uint32_t)((intptr_t)k-(intptr_t)J2G(as->J)) < 65536)
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emit_lsptr(as, LOONGI_LD_D, r64, (void *)k, 0); /*To copy a doubleword from a GPR to an FPR*/
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else
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emit_loadu64(as, r64, *k);
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}
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/* Get/set global_State fields. */
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static void emit_lsglptr2(ASMState *as, LOONGIns loongi, Reg r, int32_t ofs)
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{
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emit_djk(as, loongi, r, RID_JGL, RID_R20);
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emit_loadi(as, RID_R20, (ofs-32768));
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}
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#define emit_getgl(as, r, field) \
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emit_lsglptr2(as, LOONGI_LDX_D, (r), (int32_t)offsetof(global_State, field))
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#define emit_setgl(as, r, field) \
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emit_lsglptr2(as, LOONGI_STX_D, (r), (int32_t)offsetof(global_State, field))
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/* Trace number is determined from per-trace exit stubs. */
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#define emit_setvmstate(as, i) UNUSED(i)
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/* -- Emit control-flow instructions -------------------------------------- */
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/* Label for internal jumps. */
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typedef MCode *MCLabel;
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/* Return label pointing to current PC. */
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#define emit_label(as) ((as)->mcp)
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static void emit_branch(ASMState *as, LOONGIns loongi, Reg rj, Reg rd, MCode *target)
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{
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MCode *p = as->mcp;
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ptrdiff_t delta = target - (p - 1);
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lj_assertA(((delta + 0x8000) >> 16) == 0, "branch target out of range");
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/*BEQ BNE BGE BLZ*/
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*--p = loongi | LOONGF_D(rd) | LOONGF_J(rj) | LOONGF_I(((uint32_t)delta & 0xffffu));
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as->mcp = p;
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}
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static void emit_branch21(ASMState *as, LOONGIns loongi, Reg rj, MCode *target)
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{
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MCode *p = as->mcp;
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ptrdiff_t delta = target - (p - 1);
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lj_assertA(((delta + 0x100000) >> 21) == 0, "branch target out of range");
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*--p = loongi | LOONGF_J(rj) | LOONGF_I(((uint32_t)delta & 0xffffu))
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| (((uint32_t)delta & 0x1f0000u)>>16); /*BEQZ BNEZ BCEQZ BCNEZ*/
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as->mcp = p;
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}
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static void emit_jmp(ASMState *as, MCode *target)
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{
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MCode *p = as->mcp;
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ptrdiff_t delta = target - (p - 1);
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emit_b_bl(as, LOONGI_B, (delta&0x3ffffff)); /*offs 26*/
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}
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#define emit_move(as, dst, src) \
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emit_djk(as, LOONGI_OR, (dst), (src), RID_ZERO)
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static void emit_call(ASMState *as, void *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = (char *)target - (char *)p;
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if (LOONGF_S_OK(delta>>2, 26)) {
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*p = LOONGI_BL | LOONGF_I((delta>>2) & 0xffff) | (((delta>>2) >> 16) & 0x3ff);
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} else { /* Target out of range: need indirect call. */
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Reg r = ra_allock(as, (intptr_t)target, RSET_RANGE(RID_R12, RID_R19+1));
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*p = LOONGI_JIRL | LOONGF_D(RID_RA) | LOONGF_J(r) | LOONGF_I(0);
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}
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}
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/* -- Emit generic operations --------------------------------------------- */
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/* Generic move between two regs. */
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static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
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{
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if (dst < RID_MAX_GPR && src >= RID_MIN_FPR)
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emit_dj(as, irt_isnum(ir->t) ? LOONGI_MOVFR2GR_D : LOONGI_MOVFR2GR_S, dst, src);
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else if (dst < RID_MAX_GPR)
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emit_move(as, dst, src);
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else
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emit_dj(as, irt_isnum(ir->t) ? LOONGI_FMOV_D : LOONGI_FMOV_S, dst, src);
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}
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/* Emit an arithmetic operation with a constant operand. */
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static void emit_addk(ASMState *as, Reg dest, Reg src, int32_t i, RegSet allow)
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{
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if (checki12(i)) {
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emit_dji(as, LOONGI_ADDI_D, dest, src, i&0xfff);
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} else {
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Reg src2 = ra_allock(as, i, allow);
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emit_djk(as, LOONGI_ADD_D, dest, src, src2);
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}
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}
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static void emit_lso(ASMState *as, LOONGIns loongi, Reg dest, Reg src, int64_t i, RegSet allow)
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{
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if (checki12(i)) {
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emit_dji(as, loongi, dest, src, i&0xfff);
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} else {
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LOONGIns loongk = LOONGI_NOP;
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switch (loongi) {
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case LOONGI_LD_D: loongk = LOONGI_LDX_D; break;
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case LOONGI_LD_W: loongk = LOONGI_LDX_W; break;
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case LOONGI_ST_D: loongk = LOONGI_STX_D; break;
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case LOONGI_FLD_D: loongk = LOONGI_FLDX_D; break;
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case LOONGI_FST_D: loongk = LOONGI_FSTX_D; break;
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case LOONGI_LD_B: loongk = LOONGI_LDX_B; break;
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case LOONGI_LD_BU: loongk = LOONGI_LDX_BU; break;
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case LOONGI_LD_H: loongk = LOONGI_LDX_H; break;
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case LOONGI_LD_HU: loongk = LOONGI_LDX_HU; break;
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case LOONGI_FLD_S: loongk = LOONGI_FLDX_S; break;
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default: break;
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}
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//Reg src2 = ra_allock(as, i, allow);
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Reg src2 = ra_scratch(as, allow);
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emit_djk(as, loongk, dest, src, src2);
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emit_d16i(as, src2, i);
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}
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}
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/* Generic load of register with base and (small) offset address. */
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static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
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{
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if (r < RID_MAX_GPR) {
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emit_djk(as, irt_is64(ir->t) ? LOONGI_LDX_D : LOONGI_LDX_W, r, base, RID_R20);
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} else {
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emit_djk(as, irt_isnum(ir->t) ? LOONGI_FLDX_D : LOONGI_FLDX_S, r, base, RID_R20);
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}
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emit_d16i(as, RID_R20, ofs);
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}
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/* Generic store of register with base and (small) offset address. */
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static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
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{
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if (r < RID_MAX_GPR) {
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emit_djk(as, irt_is64(ir->t) ? LOONGI_STX_D : LOONGI_STX_W, r, base, RID_R20);
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} else {
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emit_djk(as, irt_isnum(ir->t) ? LOONGI_FSTX_D : LOONGI_FSTX_S, (r&31), base, RID_R20);
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}
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emit_d16i(as, RID_R20, ofs);
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}
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/* Add offset to pointer. */
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static void emit_addptr(ASMState *as, Reg r, int32_t ofs)
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{
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if (ofs) {
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emit_addk(as, r, r, ofs, rset_exclude(RSET_GPR, r));
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}
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}
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#define emit_spsub(as, ofs) emit_addptr(as, RID_SP, -(ofs))
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