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Decouple SLOAD type and optional conversion.
This commit is contained in:
parent
cc62edebfd
commit
b3cf2c70f4
16
lib/dump.lua
16
lib/dump.lua
@ -213,11 +213,17 @@ local colorize, irtype
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-- Lookup table to convert some literals into names.
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-- Lookup table to convert some literals into names.
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local litname = {
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local litname = {
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["SLOAD "] = { [0] = "", "I", "R", "RI", "P", "PI", "PR", "PRI",
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["SLOAD "] = setmetatable({}, { __index = function(t, mode)
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"T", "IT", "RT", "RIT", "PT", "PIT", "PRT", "PRIT",
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local s = ""
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"F", "IF", "RF", "RIF", "PF", "PIF", "PRF", "PRIF",
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if band(mode, 1) ~= 0 then s = s.."P" end
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"TF", "ITF", "RTF", "RITF", "PTF", "PITF", "PRTF", "PRITF",
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if band(mode, 2) ~= 0 then s = s.."F" end
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},
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if band(mode, 4) ~= 0 then s = s.."T" end
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if band(mode, 8) ~= 0 then s = s.."C" end
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if band(mode, 16) ~= 0 then s = s.."R" end
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if band(mode, 32) ~= 0 then s = s.."I" end
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t[mode] = s
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return s
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end}),
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["XLOAD "] = { [0] = "", "R", "U", "RU", },
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["XLOAD "] = { [0] = "", "R", "U", "RU", },
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["TOINT "] = { [0] = "check", "index", "", },
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["TOINT "] = { [0] = "check", "index", "", },
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["FLOAD "] = vmdef.irfield,
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["FLOAD "] = vmdef.irfield,
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13
src/lj_asm.c
13
src/lj_asm.c
@ -1290,8 +1290,8 @@ static Reg asm_fuseload(ASMState *as, IRRef ref, RegSet allow)
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} else if (mayfuse(as, ref)) {
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} else if (mayfuse(as, ref)) {
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RegSet xallow = (allow & RSET_GPR) ? allow : RSET_GPR;
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RegSet xallow = (allow & RSET_GPR) ? allow : RSET_GPR;
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if (ir->o == IR_SLOAD) {
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if (ir->o == IR_SLOAD) {
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if ((!irt_isint(ir->t) || (ir->op2 & IRSLOAD_FRAME)) &&
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if (!(ir->op2 & (IRSLOAD_PARENT|IRSLOAD_CONVERT)) &&
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!(ir->op2 & IRSLOAD_PARENT) && noconflict(as, ref, IR_RETF)) {
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noconflict(as, ref, IR_RETF)) {
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as->mrm.base = (uint8_t)ra_alloc1(as, REF_BASE, xallow);
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as->mrm.base = (uint8_t)ra_alloc1(as, REF_BASE, xallow);
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as->mrm.ofs = 8*((int32_t)ir->op1-1) + ((ir->op2&IRSLOAD_FRAME)?4:0);
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as->mrm.ofs = 8*((int32_t)ir->op1-1) + ((ir->op2&IRSLOAD_FRAME)?4:0);
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as->mrm.idx = RID_NONE;
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as->mrm.idx = RID_NONE;
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@ -2061,8 +2061,9 @@ static void asm_sload(ASMState *as, IRIns *ir)
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IRType1 t = ir->t;
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IRType1 t = ir->t;
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Reg base;
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Reg base;
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lua_assert(!(ir->op2 & IRSLOAD_PARENT)); /* Handled by asm_head_side(). */
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lua_assert(!(ir->op2 & IRSLOAD_PARENT)); /* Handled by asm_head_side(). */
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lua_assert(irt_isguard(ir->t) || !(ir->op2 & IRSLOAD_TYPECHECK));
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lua_assert(irt_isguard(t) || !(ir->op2 & IRSLOAD_TYPECHECK));
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if (irt_isint(t) && irt_isguard(t)) {
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lua_assert(!irt_isint(t) || (ir->op2 & (IRSLOAD_CONVERT|IRSLOAD_FRAME)));
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if ((ir->op2 & IRSLOAD_CONVERT) && irt_isguard(t)) {
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Reg left = ra_scratch(as, RSET_FPR);
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Reg left = ra_scratch(as, RSET_FPR);
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asm_tointg(as, ir, left); /* Frees dest reg. Do this before base alloc. */
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asm_tointg(as, ir, left); /* Frees dest reg. Do this before base alloc. */
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base = ra_alloc1(as, REF_BASE, RSET_GPR);
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base = ra_alloc1(as, REF_BASE, RSET_GPR);
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@ -2078,11 +2079,11 @@ static void asm_sload(ASMState *as, IRIns *ir)
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return;
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return;
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#endif
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#endif
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} else if (ra_used(ir)) {
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} else if (ra_used(ir)) {
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RegSet allow = irt_isnum(ir->t) ? RSET_FPR : RSET_GPR;
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RegSet allow = irt_isnum(t) ? RSET_FPR : RSET_GPR;
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Reg dest = ra_dest(as, ir, allow);
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Reg dest = ra_dest(as, ir, allow);
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base = ra_alloc1(as, REF_BASE, RSET_GPR);
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base = ra_alloc1(as, REF_BASE, RSET_GPR);
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lua_assert(irt_isnum(t) || irt_isint(t) || irt_isaddr(t));
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lua_assert(irt_isnum(t) || irt_isint(t) || irt_isaddr(t));
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if (irt_isint(t) && !(ir->op2 & IRSLOAD_FRAME))
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if ((ir->op2 & IRSLOAD_CONVERT))
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emit_rmro(as, XO_CVTSD2SI, dest, base, ofs);
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emit_rmro(as, XO_CVTSD2SI, dest, base, ofs);
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else if (irt_isnum(t))
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else if (irt_isnum(t))
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emit_rmro(as, XMM_MOVRM(as), dest, base, ofs);
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emit_rmro(as, XMM_MOVRM(as), dest, base, ofs);
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11
src/lj_ir.h
11
src/lj_ir.h
@ -190,11 +190,12 @@ IRFLDEF(FLENUM)
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} IRFieldID;
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} IRFieldID;
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/* SLOAD mode bits, stored in op2. */
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/* SLOAD mode bits, stored in op2. */
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#define IRSLOAD_INHERIT 0x01 /* Inherited by exits/side traces. */
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#define IRSLOAD_PARENT 0x01 /* Coalesce with parent trace. */
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#define IRSLOAD_READONLY 0x02 /* Read-only, omit slot store. */
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#define IRSLOAD_FRAME 0x02 /* Load hiword of frame. */
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#define IRSLOAD_PARENT 0x04 /* Coalesce with parent trace. */
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#define IRSLOAD_TYPECHECK 0x04 /* Needs type check. */
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#define IRSLOAD_TYPECHECK 0x08 /* Needs type check. */
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#define IRSLOAD_CONVERT 0x08 /* Number to integer conversion. */
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#define IRSLOAD_FRAME 0x10 /* Load hiword of frame. */
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#define IRSLOAD_READONLY 0x10 /* Read-only, omit slot store. */
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#define IRSLOAD_INHERIT 0x20 /* Inherited by exits/side traces. */
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/* XLOAD mode, stored in op2. */
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/* XLOAD mode, stored in op2. */
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#define IRXLOAD_READONLY 1 /* Load from read-only data. */
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#define IRXLOAD_READONLY 1 /* Load from read-only data. */
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@ -218,7 +218,7 @@ typedef struct ScEvEntry {
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IRRef1 stop; /* Constant stop reference. */
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IRRef1 stop; /* Constant stop reference. */
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IRRef1 step; /* Constant step reference. */
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IRRef1 step; /* Constant step reference. */
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IRType1 t; /* Scalar type. */
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IRType1 t; /* Scalar type. */
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uint8_t dir; /* Direction. 0: +, 1: -. */
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uint8_t dir; /* Direction. 1: +, 0: -. */
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} ScEvEntry;
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} ScEvEntry;
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/* 128 bit SIMD constants. */
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/* 128 bit SIMD constants. */
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@ -298,11 +298,11 @@ static TRef fori_arg(jit_State *J, const BCIns *fori, BCReg slot, IRType t)
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TRef tr = J->base[slot];
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TRef tr = J->base[slot];
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if (!tr) {
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if (!tr) {
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tr = find_kinit(J, fori, slot, t);
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tr = find_kinit(J, fori, slot, t);
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if (!tr) {
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if (!tr)
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if (t == IRT_INT)
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tr = sloadt(J, (int32_t)slot,
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t |= IRT_GUARD;
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t == IRT_INT ? (IRT_INT|IRT_GUARD) : t,
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tr = sloadt(J, (int32_t)slot, t, IRSLOAD_READONLY|IRSLOAD_INHERIT);
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t == IRT_INT ? (IRSLOAD_CONVERT|IRSLOAD_READONLY|IRSLOAD_INHERIT) :
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}
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(IRSLOAD_READONLY|IRSLOAD_INHERIT));
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}
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}
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return tr;
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return tr;
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}
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}
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@ -2512,6 +2512,7 @@ static void rec_setup_forl(jit_State *J, const BCIns *fori)
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cTValue *forbase = &J->L->base[ra];
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cTValue *forbase = &J->L->base[ra];
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IRType t = (J->flags & JIT_F_OPT_NARROW) ? lj_opt_narrow_forl(forbase)
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IRType t = (J->flags & JIT_F_OPT_NARROW) ? lj_opt_narrow_forl(forbase)
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: IRT_NUM;
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: IRT_NUM;
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TRef start;
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TRef stop = fori_arg(J, fori, ra+FORL_STOP, t);
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TRef stop = fori_arg(J, fori, ra+FORL_STOP, t);
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TRef step = fori_arg(J, fori, ra+FORL_STEP, t);
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TRef step = fori_arg(J, fori, ra+FORL_STEP, t);
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int dir = (0 <= numV(&forbase[FORL_STEP]));
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int dir = (0 <= numV(&forbase[FORL_STEP]));
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@ -2548,10 +2549,11 @@ static void rec_setup_forl(jit_State *J, const BCIns *fori)
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emitir(IRTGI(dir ? IR_LE : IR_GE), stop, lj_ir_kint(J, k));
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emitir(IRTGI(dir ? IR_LE : IR_GE), stop, lj_ir_kint(J, k));
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}
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}
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J->scev.start = tref_ref(find_kinit(J, fori, ra+FORL_IDX, IRT_INT));
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J->scev.start = tref_ref(find_kinit(J, fori, ra+FORL_IDX, IRT_INT));
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if (t == IRT_INT && !J->scev.start)
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start = sloadt(J, (int32_t)(ra+FORL_IDX),
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t |= IRT_GUARD;
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(t == IRT_INT && !J->scev.start) ? (IRT_INT|IRT_GUARD) : t,
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J->base[ra+FORL_EXT] = sloadt(J, (int32_t)(ra+FORL_IDX), t, IRSLOAD_INHERIT);
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t == IRT_INT ? (IRSLOAD_CONVERT|IRSLOAD_INHERIT) : IRSLOAD_INHERIT);
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J->scev.idx = tref_ref(J->base[ra+FORL_EXT]);
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J->base[ra+FORL_EXT] = start;
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J->scev.idx = tref_ref(start);
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J->maxslot = ra+FORL_EXT+1;
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J->maxslot = ra+FORL_EXT+1;
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}
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}
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