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Add generic load/store with offset to assembler backends.

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This commit is contained in:
Mike Pall 2013-04-21 00:58:32 +02:00
parent e92e29dd4e
commit 9ead735159
6 changed files with 39 additions and 32 deletions
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6
src/lj_asm.c
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@ -179,6 +179,12 @@ IRFLDEF(FLOFS)
#error "Missing instruction emitter for target CPU"
#endif
/* Generic load/store of register from/to stack slot. */
#define emit_spload(as, ir, r, ofs) \
emit_loadofs(as, ir, (r), RID_SP, (ofs))
#define emit_spstore(as, ir, r, ofs) \
emit_storeofs(as, ir, (r), RID_SP, (ofs))
/* -- Register allocator debugging ---------------------------------------- */
/* #define LUAJIT_DEBUG_RA */

16
src/lj_emit_arm.h
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@ -308,30 +308,30 @@ static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
emit_dm(as, ARMI_MOV, dst, src);
}
/* Generic load of register from stack slot. */
static void emit_spload(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
/* Generic load of register with base and (small) offset address. */
static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
{
#if LJ_SOFTFP
lua_assert(!irt_isnum(ir->t)); UNUSED(ir);
#else
if (r >= RID_MAX_GPR)
emit_vlso(as, irt_isnum(ir->t) ? ARMI_VLDR_D : ARMI_VLDR_S, r, RID_SP, ofs);
emit_vlso(as, irt_isnum(ir->t) ? ARMI_VLDR_D : ARMI_VLDR_S, r, base, ofs);
else
#endif
emit_lso(as, ARMI_LDR, r, RID_SP, ofs);
emit_lso(as, ARMI_LDR, r, base, ofs);
}
/* Generic store of register to stack slot. */
static void emit_spstore(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
/* Generic store of register with base and (small) offset address. */
static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
{
#if LJ_SOFTFP
lua_assert(!irt_isnum(ir->t)); UNUSED(ir);
#else
if (r >= RID_MAX_GPR)
emit_vlso(as, irt_isnum(ir->t) ? ARMI_VSTR_D : ARMI_VSTR_S, r, RID_SP, ofs);
emit_vlso(as, irt_isnum(ir->t) ? ARMI_VSTR_D : ARMI_VSTR_S, r, base, ofs);
else
#endif
emit_lso(as, ARMI_STR, r, RID_SP, ofs);
emit_lso(as, ARMI_STR, r, base, ofs);
}
/* Emit an arithmetic/logic operation with a constant operand. */

16
src/lj_emit_mips.h
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@ -178,24 +178,24 @@ static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
emit_fg(as, irt_isnum(ir->t) ? MIPSI_MOV_D : MIPSI_MOV_S, dst, src);
}
/* Generic load of register from stack slot. */
static void emit_spload(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
/* Generic load of register with base and (small) offset address. */
static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
{
if (r < RID_MAX_GPR)
emit_tsi(as, MIPSI_LW, r, RID_SP, ofs);
emit_tsi(as, MIPSI_LW, r, base, ofs);
else
emit_tsi(as, irt_isnum(ir->t) ? MIPSI_LDC1 : MIPSI_LWC1,
(r & 31), RID_SP, ofs);
(r & 31), base, ofs);
}
/* Generic store of register to stack slot. */
static void emit_spstore(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
/* Generic store of register with base and (small) offset address. */
static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
{
if (r < RID_MAX_GPR)
emit_tsi(as, MIPSI_SW, r, RID_SP, ofs);
emit_tsi(as, MIPSI_SW, r, base, ofs);
else
emit_tsi(as, irt_isnum(ir->t) ? MIPSI_SDC1 : MIPSI_SWC1,
(r&31), RID_SP, ofs);
(r&31), base, ofs);
}
/* Add offset to pointer. */

16
src/lj_emit_ppc.h
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@ -186,22 +186,22 @@ static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
emit_fb(as, PPCI_FMR, dst, src);
}
/* Generic load of register from stack slot. */
static void emit_spload(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
/* Generic load of register with base and (small) offset address. */
static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
{
if (r < RID_MAX_GPR)
emit_tai(as, PPCI_LWZ, r, RID_SP, ofs);
emit_tai(as, PPCI_LWZ, r, base, ofs);
else
emit_fai(as, irt_isnum(ir->t) ? PPCI_LFD : PPCI_LFS, r, RID_SP, ofs);
emit_fai(as, irt_isnum(ir->t) ? PPCI_LFD : PPCI_LFS, r, base, ofs);
}
/* Generic store of register to stack slot. */
static void emit_spstore(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
/* Generic store of register with base and (small) offset address. */
static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
{
if (r < RID_MAX_GPR)
emit_tai(as, PPCI_STW, r, RID_SP, ofs);
emit_tai(as, PPCI_STW, r, base, ofs);
else
emit_fai(as, irt_isnum(ir->t) ? PPCI_STFD : PPCI_STFS, r, RID_SP, ofs);
emit_fai(as, irt_isnum(ir->t) ? PPCI_STFD : PPCI_STFS, r, base, ofs);
}
/* Emit a compare (for equality) with a constant operand. */

16
src/lj_emit_x86.h
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@ -426,22 +426,22 @@ static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
emit_rr(as, XO_MOVAPS, dst, src);
}
/* Generic load of register from stack slot. */
static void emit_spload(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
/* Generic load of register with base and (small) offset address. */
static void emit_loadofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
{
if (r < RID_MAX_GPR)
emit_rmro(as, XO_MOV, REX_64IR(ir, r), RID_ESP, ofs);
emit_rmro(as, XO_MOV, REX_64IR(ir, r), base, ofs);
else
emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSD : XO_MOVSS, r, RID_ESP, ofs);
emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSD : XO_MOVSS, r, base, ofs);
}
/* Generic store of register to stack slot. */
static void emit_spstore(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
/* Generic store of register with base and (small) offset address. */
static void emit_storeofs(ASMState *as, IRIns *ir, Reg r, Reg base, int32_t ofs)
{
if (r < RID_MAX_GPR)
emit_rmro(as, XO_MOVto, REX_64IR(ir, r), RID_ESP, ofs);
emit_rmro(as, XO_MOVto, REX_64IR(ir, r), base, ofs);
else
emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSDto : XO_MOVSSto, r, RID_ESP, ofs);
emit_rmro(as, irt_isnum(ir->t) ? XO_MOVSDto : XO_MOVSSto, r, base, ofs);
}
/* Add offset to pointer. */

1
src/lj_target_x86.h
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@ -33,6 +33,7 @@ enum {
RID_MRM = RID_MAX, /* Pseudo-id for ModRM operand. */
/* Calling conventions. */
RID_SP = RID_ESP,
RID_RET = RID_EAX,
#if LJ_64
RID_FPRET = RID_XMM0,