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https://github.com/LuaJIT/LuaJIT.git
synced 2025-02-07 15:14:08 +00:00
Merge branch 'master' into v2.1
This commit is contained in:
commit
8635cbabf3
@ -1889,6 +1889,7 @@ static void asm_head_side(ASMState *as)
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RegSet allow = RSET_ALL; /* Inverse of all coalesced registers. */
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RegSet allow = RSET_ALL; /* Inverse of all coalesced registers. */
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RegSet live = RSET_EMPTY; /* Live parent registers. */
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RegSet live = RSET_EMPTY; /* Live parent registers. */
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RegSet pallow = RSET_GPR; /* Registers needed by the parent stack check. */
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RegSet pallow = RSET_GPR; /* Registers needed by the parent stack check. */
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Reg pbase;
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IRIns *irp = &as->parent->ir[REF_BASE]; /* Parent base. */
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IRIns *irp = &as->parent->ir[REF_BASE]; /* Parent base. */
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int32_t spadj, spdelta;
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int32_t spadj, spdelta;
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int pass2 = 0;
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int pass2 = 0;
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@ -1899,7 +1900,11 @@ static void asm_head_side(ASMState *as)
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/* Force snap #0 alloc to prevent register overwrite in stack check. */
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/* Force snap #0 alloc to prevent register overwrite in stack check. */
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asm_snap_alloc(as, 0);
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asm_snap_alloc(as, 0);
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}
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}
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allow = asm_head_side_base(as, irp, allow);
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pbase = asm_head_side_base(as, irp);
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if (pbase != RID_NONE) {
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rset_clear(allow, pbase);
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rset_clear(pallow, pbase);
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}
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/* Scan all parent SLOADs and collect register dependencies. */
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/* Scan all parent SLOADs and collect register dependencies. */
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for (i = as->stopins; i > REF_BASE; i--) {
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for (i = as->stopins; i > REF_BASE; i--) {
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@ -2167,7 +2167,7 @@ static void asm_head_root_base(ASMState *as)
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}
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}
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/* Coalesce BASE register for a side trace. */
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/* Coalesce BASE register for a side trace. */
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static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
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static Reg asm_head_side_base(ASMState *as, IRIns *irp)
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{
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{
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IRIns *ir;
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IRIns *ir;
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asm_head_lreg(as);
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asm_head_lreg(as);
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@ -2175,16 +2175,15 @@ static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
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if (ra_hasreg(ir->r) && (rset_test(as->modset, ir->r) || irt_ismarked(ir->t)))
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if (ra_hasreg(ir->r) && (rset_test(as->modset, ir->r) || irt_ismarked(ir->t)))
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ra_spill(as, ir);
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ra_spill(as, ir);
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if (ra_hasspill(irp->s)) {
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if (ra_hasspill(irp->s)) {
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rset_clear(allow, ra_dest(as, ir, allow));
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return ra_dest(as, ir, RSET_GPR);
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} else {
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} else {
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Reg r = irp->r;
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Reg r = irp->r;
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lj_assertA(ra_hasreg(r), "base reg lost");
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lj_assertA(ra_hasreg(r), "base reg lost");
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rset_clear(allow, r);
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if (r != ir->r && !rset_test(as->freeset, r))
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if (r != ir->r && !rset_test(as->freeset, r))
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ra_restore(as, regcost_ref(as->cost[r]));
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ra_restore(as, regcost_ref(as->cost[r]));
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ra_destreg(as, ir, r);
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ra_destreg(as, ir, r);
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return r;
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}
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}
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return allow;
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}
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}
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/* -- Tail of trace ------------------------------------------------------- */
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/* -- Tail of trace ------------------------------------------------------- */
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@ -1915,7 +1915,7 @@ static void asm_head_root_base(ASMState *as)
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}
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}
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/* Coalesce BASE register for a side trace. */
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/* Coalesce BASE register for a side trace. */
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static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
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static Reg asm_head_side_base(ASMState *as, IRIns *irp)
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{
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{
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IRIns *ir;
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IRIns *ir;
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asm_head_lreg(as);
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asm_head_lreg(as);
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@ -1923,16 +1923,15 @@ static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
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if (ra_hasreg(ir->r) && (rset_test(as->modset, ir->r) || irt_ismarked(ir->t)))
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if (ra_hasreg(ir->r) && (rset_test(as->modset, ir->r) || irt_ismarked(ir->t)))
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ra_spill(as, ir);
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ra_spill(as, ir);
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if (ra_hasspill(irp->s)) {
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if (ra_hasspill(irp->s)) {
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rset_clear(allow, ra_dest(as, ir, allow));
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return ra_dest(as, ir, RSET_GPR);
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} else {
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} else {
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Reg r = irp->r;
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Reg r = irp->r;
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lj_assertA(ra_hasreg(r), "base reg lost");
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lj_assertA(ra_hasreg(r), "base reg lost");
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rset_clear(allow, r);
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if (r != ir->r && !rset_test(as->freeset, r))
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if (r != ir->r && !rset_test(as->freeset, r))
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ra_restore(as, regcost_ref(as->cost[r]));
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ra_restore(as, regcost_ref(as->cost[r]));
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ra_destreg(as, ir, r);
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ra_destreg(as, ir, r);
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return r;
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}
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}
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return allow;
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}
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}
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/* -- Tail of trace ------------------------------------------------------- */
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/* -- Tail of trace ------------------------------------------------------- */
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@ -2667,7 +2667,7 @@ static void asm_head_root_base(ASMState *as)
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}
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}
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/* Coalesce BASE register for a side trace. */
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/* Coalesce BASE register for a side trace. */
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static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
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static Reg asm_head_side_base(ASMState *as, IRIns *irp)
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{
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{
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IRIns *ir = IR(REF_BASE);
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IRIns *ir = IR(REF_BASE);
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Reg r = ir->r;
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Reg r = ir->r;
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@ -2676,15 +2676,15 @@ static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
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if (rset_test(as->modset, r) || irt_ismarked(ir->t))
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if (rset_test(as->modset, r) || irt_ismarked(ir->t))
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ir->r = RID_INIT; /* No inheritance for modified BASE register. */
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ir->r = RID_INIT; /* No inheritance for modified BASE register. */
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if (irp->r == r) {
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if (irp->r == r) {
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rset_clear(allow, r); /* Mark same BASE register as coalesced. */
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return r; /* Same BASE register already coalesced. */
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} else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
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} else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
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rset_clear(allow, irp->r);
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emit_move(as, r, irp->r); /* Move from coalesced parent reg. */
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emit_move(as, r, irp->r); /* Move from coalesced parent reg. */
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return irp->r;
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} else {
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} else {
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emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
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emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
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}
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}
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}
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}
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return allow;
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return RID_NONE;
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}
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}
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/* -- Tail of trace ------------------------------------------------------- */
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/* -- Tail of trace ------------------------------------------------------- */
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@ -2186,7 +2186,7 @@ static void asm_head_root_base(ASMState *as)
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}
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}
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/* Coalesce BASE register for a side trace. */
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/* Coalesce BASE register for a side trace. */
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static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
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static Reg asm_head_side_base(ASMState *as, IRIns *irp)
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{
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{
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IRIns *ir = IR(REF_BASE);
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IRIns *ir = IR(REF_BASE);
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Reg r = ir->r;
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Reg r = ir->r;
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@ -2195,15 +2195,15 @@ static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
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if (rset_test(as->modset, r) || irt_ismarked(ir->t))
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if (rset_test(as->modset, r) || irt_ismarked(ir->t))
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ir->r = RID_INIT; /* No inheritance for modified BASE register. */
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ir->r = RID_INIT; /* No inheritance for modified BASE register. */
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if (irp->r == r) {
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if (irp->r == r) {
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rset_clear(allow, r); /* Mark same BASE register as coalesced. */
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return r; /* Same BASE register already coalesced. */
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} else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
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} else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
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rset_clear(allow, irp->r);
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emit_mr(as, r, irp->r); /* Move from coalesced parent reg. */
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emit_mr(as, r, irp->r); /* Move from coalesced parent reg. */
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return irp->r;
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} else {
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} else {
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emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
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emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
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}
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}
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}
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}
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return allow;
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return RID_NONE;
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}
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}
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/* -- Tail of trace ------------------------------------------------------- */
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/* -- Tail of trace ------------------------------------------------------- */
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@ -2877,7 +2877,7 @@ static void asm_head_root_base(ASMState *as)
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}
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}
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/* Coalesce or reload BASE register for a side trace. */
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/* Coalesce or reload BASE register for a side trace. */
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static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
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static Reg asm_head_side_base(ASMState *as, IRIns *irp)
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{
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{
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IRIns *ir = IR(REF_BASE);
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IRIns *ir = IR(REF_BASE);
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Reg r = ir->r;
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Reg r = ir->r;
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@ -2886,16 +2886,16 @@ static RegSet asm_head_side_base(ASMState *as, IRIns *irp, RegSet allow)
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if (rset_test(as->modset, r) || irt_ismarked(ir->t))
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if (rset_test(as->modset, r) || irt_ismarked(ir->t))
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ir->r = RID_INIT; /* No inheritance for modified BASE register. */
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ir->r = RID_INIT; /* No inheritance for modified BASE register. */
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if (irp->r == r) {
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if (irp->r == r) {
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rset_clear(allow, r); /* Mark same BASE register as coalesced. */
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return r; /* Same BASE register already coalesced. */
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} else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
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} else if (ra_hasreg(irp->r) && rset_test(as->freeset, irp->r)) {
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/* Move from coalesced parent reg. */
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/* Move from coalesced parent reg. */
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rset_clear(allow, irp->r);
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emit_rr(as, XO_MOV, r|REX_GC64, irp->r);
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emit_rr(as, XO_MOV, r|REX_GC64, irp->r);
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return irp->r;
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} else {
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} else {
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emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
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emit_getgl(as, r, jit_base); /* Otherwise reload BASE. */
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}
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}
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}
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}
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return allow;
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return RID_NONE;
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}
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}
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/* -- Tail of trace ------------------------------------------------------- */
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/* -- Tail of trace ------------------------------------------------------- */
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