x64/LJ_GC64: Fix emit_rma().

This commit is contained in:
Mike Pall 2017-07-26 09:52:53 +02:00
parent cf2dfaf3b4
commit 7e662e4f87

View File

@ -343,9 +343,27 @@ static void emit_rma(ASMState *as, x86Op xo, Reg rr, const void *addr)
emit_rmro(as, xo, rr, RID_DISPATCH, (int32_t)dispofs(as, addr));
} else if (checki32(mcpofs(as, addr)) && checki32(mctopofs(as, addr))) {
emit_rmro(as, xo, rr, RID_RIP, (int32_t)mcpofs(as, addr));
} else if (!checki32((intptr_t)addr) && (xo == XO_MOV || xo == XO_MOVSD)) {
emit_rmro(as, xo, rr, rr, 0);
emit_loadu64(as, rr, (uintptr_t)addr);
} else if (!checki32((intptr_t)addr)) {
Reg ra = (rr & 15);
if (xo != XO_MOV) {
/* We can't allocate a register here. Use and restore DISPATCH. Ugly. */
uint64_t dispaddr = (uintptr_t)J2GG(as->J)->dispatch;
uint8_t i8 = xo == XO_GROUP3b ? *as->mcp++ : 0;
ra = RID_DISPATCH;
if (checku32(dispaddr)) {
emit_loadi(as, ra, (int32_t)dispaddr);
} else { /* Full-size 64 bit load. */
MCode *p = as->mcp;
*(uint64_t *)(p-8) = dispaddr;
p[-9] = (MCode)(XI_MOVri+(ra&7));
p[-10] = 0x48 + ((ra>>3)&1);
p -= 10;
as->mcp = p;
}
if (xo == XO_GROUP3b) emit_i8(as, i8);
}
emit_rmro(as, xo, rr, ra, 0);
emit_loadu64(as, ra, (uintptr_t)addr);
} else
#endif
{