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Extended emit_op to support 4 byte opcodes based on checking a new flag OP4B in rr
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@ -26,6 +26,8 @@
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#define REX_GC64 0
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#define REX_GC64 0
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#endif
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#endif
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#define OP4B 0x4000
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#define VEX_256 0x40000
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#define VEX_256 0x40000
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/* msb is also set to c5 so we can spot a vex op in op_emit */
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/* msb is also set to c5 so we can spot a vex op in op_emit */
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@ -76,6 +78,8 @@ static LJ_AINLINE MCode *emit_op(x86Op xo, Reg rr, Reg rb, Reg rx,
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int n = (int8_t)xo;
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int n = (int8_t)xo;
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if ((n + 58) <= 0) { /* VEX-encoded instruction */
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if ((n + 58) <= 0) { /* VEX-encoded instruction */
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return emit_vop(xo, rr, rb, rx, p, delta);
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return emit_vop(xo, rr, rb, rx, p, delta);
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} else if (rr & OP4B) {
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n = -5;
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}
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}
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#if defined(__GNUC__)
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#if defined(__GNUC__)
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if (__builtin_constant_p(xo) && n == -2)
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if (__builtin_constant_p(xo) && n == -2)
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@ -92,6 +96,7 @@ static LJ_AINLINE MCode *emit_op(x86Op xo, Reg rr, Reg rb, Reg rx,
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if (rex != 0x40) {
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if (rex != 0x40) {
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rex |= (rr >> 16);
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rex |= (rr >> 16);
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if (n == -4) { *p = (MCode)rex; rex = (MCode)(xo >> 8); }
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if (n == -4) { *p = (MCode)rex; rex = (MCode)(xo >> 8); }
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else if (n == -5) { *p = (MCode)rex; rex = (MCode)(xo); }
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else if ((xo & 0xffffff) == 0x6600fd) { *p = (MCode)rex; rex = 0x66; }
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else if ((xo & 0xffffff) == 0x6600fd) { *p = (MCode)rex; rex = 0x66; }
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*--p = (MCode)rex;
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*--p = (MCode)rex;
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}
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}
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