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Merge branch 'master' into v2.1

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This commit is contained in:
Mike Pall 2023-07-08 19:43:08 +02:00
commit 69dadad6c3
3 changed files with 5 additions and 4 deletions
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2
src/lib_ffi.c
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@ -776,7 +776,7 @@ LJLIB_CF(ffi_metatype)
if (!(ctype_isstruct(ct->info) || ctype_iscomplex(ct->info) || if (!(ctype_isstruct(ct->info) || ctype_iscomplex(ct->info) ||
ctype_isvector(ct->info))) ctype_isvector(ct->info)))
lj_err_arg(L, 1, LJ_ERR_FFI_INVTYPE); lj_err_arg(L, 1, LJ_ERR_FFI_INVTYPE);
tv = lj_tab_setinth(L, t, -(int32_t)id); tv = lj_tab_setinth(L, t, -(int32_t)ctype_typeid(cts, ct));
if (!tvisnil(tv)) if (!tvisnil(tv))
lj_err_caller(L, LJ_ERR_PROTMT); lj_err_caller(L, LJ_ERR_PROTMT);
settabV(L, tv, mt); settabV(L, tv, mt);

4
src/lj_asm.c
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@ -1888,6 +1888,7 @@ static void asm_head_side(ASMState *as)
IRRef1 sloadins[RID_MAX]; IRRef1 sloadins[RID_MAX];
RegSet allow = RSET_ALL; /* Inverse of all coalesced registers. */ RegSet allow = RSET_ALL; /* Inverse of all coalesced registers. */
RegSet live = RSET_EMPTY; /* Live parent registers. */ RegSet live = RSET_EMPTY; /* Live parent registers. */
RegSet pallow = RSET_GPR; /* Registers needed by the parent stack check. */
IRIns *irp = &as->parent->ir[REF_BASE]; /* Parent base. */ IRIns *irp = &as->parent->ir[REF_BASE]; /* Parent base. */
int32_t spadj, spdelta; int32_t spadj, spdelta;
int pass2 = 0; int pass2 = 0;
@ -1928,6 +1929,7 @@ static void asm_head_side(ASMState *as)
sloadins[rs] = (IRRef1)i; sloadins[rs] = (IRRef1)i;
rset_set(live, rs); /* Block live parent register. */ rset_set(live, rs); /* Block live parent register. */
} }
if (!ra_hasspill(regsp_spill(rs))) rset_clear(pallow, regsp_reg(rs));
} }
/* Calculate stack frame adjustment. */ /* Calculate stack frame adjustment. */
@ -2044,7 +2046,7 @@ static void asm_head_side(ASMState *as)
ExitNo exitno = as->J->exitno; ExitNo exitno = as->J->exitno;
#endif #endif
as->T->topslot = (uint8_t)as->topslot; /* Remember for child traces. */ as->T->topslot = (uint8_t)as->topslot; /* Remember for child traces. */
asm_stack_check(as, as->topslot, irp, allow & RSET_GPR, exitno); asm_stack_check(as, as->topslot, irp, pallow, exitno);
} }
} }

3
src/lj_record.c
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@ -1976,8 +1976,7 @@ static void rec_varg(jit_State *J, BCReg dst, ptrdiff_t nresults)
} }
for (i = nvararg; i < nresults; i++) for (i = nvararg; i < nresults; i++)
J->base[dst+i] = TREF_NIL; J->base[dst+i] = TREF_NIL;
if (dst + (BCReg)nresults > J->maxslot) J->maxslot = dst + (BCReg)nresults;
J->maxslot = dst + (BCReg)nresults;
} else if (select_detect(J)) { /* y = select(x, ...) */ } else if (select_detect(J)) { /* y = select(x, ...) */
TRef tridx = J->base[dst-1]; TRef tridx = J->base[dst-1];
TRef tr = TREF_NIL; TRef tr = TREF_NIL;