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ARM: Fix stack check for spilled BASE in parent.

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This commit is contained in:
Mike Pall 2011-12-10 00:18:19 +01:00
parent 2591b4524a
commit 60b8e9e2fb
1 changed files with 5 additions and 7 deletions
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12
src/lj_asm_arm.h
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@ -1422,8 +1422,9 @@ static void asm_stack_check(ASMState *as, BCReg topslot,
Reg pbase; Reg pbase;
uint32_t k; uint32_t k;
if (irp) { if (irp) {
if (ra_hasreg(irp->r)) { if (!ra_hasspill(irp->s)) {
pbase = irp->r; pbase = irp->r;
lua_assert(ra_hasreg(pbase));
} else if (allow) { } else if (allow) {
pbase = rset_pickbot(allow); pbase = rset_pickbot(allow);
} else { } else {
@ -1442,14 +1443,11 @@ static void asm_stack_check(ASMState *as, BCReg topslot,
(int32_t)offsetof(lua_State, maxstack)); (int32_t)offsetof(lua_State, maxstack));
if (irp) { /* Must not spill arbitrary registers in head of side trace. */ if (irp) { /* Must not spill arbitrary registers in head of side trace. */
int32_t i = i32ptr(&J2G(as->J)->jit_L); int32_t i = i32ptr(&J2G(as->J)->jit_L);
if (ra_noreg(irp->r)) { if (ra_hasspill(irp->s))
lua_assert(ra_hasspill(irp->s)); emit_lso(as, ARMI_LDR, pbase, RID_SP, sps_scale(irp->s));
emit_lso(as, ARMI_LDR, RID_RET, RID_SP, sps_scale(irp->s));
}
emit_lso(as, ARMI_LDR, RID_TMP, RID_TMP, (i & 4095)); emit_lso(as, ARMI_LDR, RID_TMP, RID_TMP, (i & 4095));
if (ra_noreg(irp->r)) { if (ra_hasspill(irp->s) && !allow)
emit_lso(as, ARMI_STR, RID_RET, RID_SP, 0); /* Save temp. register. */ emit_lso(as, ARMI_STR, RID_RET, RID_SP, 0); /* Save temp. register. */
}
emit_loadi(as, RID_TMP, (i & ~4095)); emit_loadi(as, RID_TMP, (i & ~4095));
} else { } else {
emit_getgl(as, RID_TMP, jit_L); emit_getgl(as, RID_TMP, jit_L);