mirror of
https://github.com/LuaJIT/LuaJIT.git
synced 2025-02-12 17:24:09 +00:00
ARM: Add ARM-specific assembler backend.
This commit is contained in:
Mike Pall
parent
fff2fb31f9
commit
5d82cfd091
@ -159,6 +159,8 @@ IRFLDEF(FLOFS)
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#if LJ_TARGET_X86ORX64
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#include "lj_emit_x86.h"
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#elif LJ_TARGET_ARM
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#include "lj_emit_arm.h"
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#else
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#error "Missing instruction emitter for target CPU"
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#endif
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@ -1098,6 +1100,8 @@ static void asm_loop(ASMState *as)
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#if LJ_TARGET_X86ORX64
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#include "lj_asm_x86.h"
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#elif LJ_TARGET_ARM
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#include "lj_asm_arm.h"
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#else
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#error "Missing instruction emitter for target CPU"
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#endif
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1763
src/lj_asm_arm.h
Normal file
1763
src/lj_asm_arm.h
Normal file
File diff suppressed because it is too large
Load Diff
300
src/lj_emit_arm.h
Normal file
300
src/lj_emit_arm.h
Normal file
@ -0,0 +1,300 @@
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/*
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** ARM instruction emitter.
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** Copyright (C) 2005-2011 Mike Pall. See Copyright Notice in luajit.h
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*/
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/* -- Constant encoding --------------------------------------------------- */
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static uint8_t emit_invai[16] = {
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/* AND */ (ARMI_AND^ARMI_BIC) >> 21,
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/* EOR */ 0,
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/* SUB */ (ARMI_SUB^ARMI_ADD) >> 21,
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/* RSB */ 0,
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/* ADD */ (ARMI_ADD^ARMI_SUB) >> 21,
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/* ADC */ (ARMI_ADC^ARMI_SBC) >> 21,
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/* SBC */ (ARMI_SBC^ARMI_ADC) >> 21,
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/* RSC */ 0,
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/* TST */ 0,
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/* TEQ */ 0,
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/* CMP */ (ARMI_CMP^ARMI_CMN) >> 21,
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/* CMN */ (ARMI_CMN^ARMI_CMP) >> 21,
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/* ORR */ 0,
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/* MOV */ (ARMI_MOV^ARMI_MVN) >> 21,
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/* BIC */ (ARMI_BIC^ARMI_AND) >> 21,
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/* MVN */ (ARMI_MVN^ARMI_MOV) >> 21
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};
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/* Encode constant in K12 format for data processing instructions. */
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static uint32_t emit_isk12(ARMIns ai, int32_t n)
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{
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uint32_t invai, i, m = (uint32_t)n;
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/* K12: unsigned 8 bit value, rotated in steps of two bits. */
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for (i = 0; i < 4096; i += 256, m = lj_rol(m, 2))
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if (m <= 255) return ARMI_K12|m|i;
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/* Otherwise try negation/complement with the inverse instruction. */
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invai = emit_invai[((ai >> 21) & 15)];
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if (!invai) return 0; /* Failed. No inverse instruction. */
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m = ~(uint32_t)n;
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if (invai == ((ARMI_SUB^ARMI_ADD) >> 21) ||
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invai == (ARMI_CMP^ARMI_CMN) >> 21) m++;
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for (i = 0; i < 4096; i += 256, m = lj_rol(m, 2))
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if (m <= 255) return ARMI_K12|(invai<<21)|m|i;
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return 0; /* Failed. */
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}
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/* -- Emit basic instructions --------------------------------------------- */
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static void emit_dnm(ASMState *as, ARMIns ai, Reg rd, Reg rn, Reg rm)
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{
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*--as->mcp = ai | ARMF_D(rd) | ARMF_N(rn) | ARMF_M(rm);
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}
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static void emit_dm(ASMState *as, ARMIns ai, Reg rd, Reg rm)
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{
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*--as->mcp = ai | ARMF_D(rd) | ARMF_M(rm);
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}
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static void emit_dn(ASMState *as, ARMIns ai, Reg rd, Reg rn)
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{
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*--as->mcp = ai | ARMF_D(rd) | ARMF_N(rn);
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}
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static void emit_nm(ASMState *as, ARMIns ai, Reg rn, Reg rm)
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{
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*--as->mcp = ai | ARMF_N(rn) | ARMF_M(rm);
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}
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static void emit_d(ASMState *as, ARMIns ai, Reg rd)
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{
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*--as->mcp = ai | ARMF_D(rd);
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}
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static void emit_n(ASMState *as, ARMIns ai, Reg rn)
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{
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*--as->mcp = ai | ARMF_N(rn);
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}
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static void emit_m(ASMState *as, ARMIns ai, Reg rm)
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{
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*--as->mcp = ai | ARMF_M(rm);
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}
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static void emit_lsox(ASMState *as, ARMIns ai, Reg rd, Reg rn, int32_t ofs)
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{
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lua_assert(ofs >= -255 && ofs <= 255);
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if (ofs < 0) ofs = -ofs; else ai |= ARMI_LS_U;
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*--as->mcp = ai | ARMI_LS_P | ARMI_LSX_I | ARMF_D(rd) | ARMF_N(rn) |
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((ofs & 0xf0) << 4) | (ofs & 0x0f);
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}
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static void emit_lso(ASMState *as, ARMIns ai, Reg rd, Reg rn, int32_t ofs)
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{
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lua_assert(ofs >= -4095 && ofs <= 4095);
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/* Combine LDR/STR pairs to LDRD/STRD. */
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if (*as->mcp == (ai|ARMI_LS_P|ARMI_LS_U|ARMF_D(rd^1)|ARMF_N(rn)|(ofs^4)) &&
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(ai & ~(ARMI_LDR^ARMI_STR)) == ARMI_STR && rd != rn &&
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(uint32_t)ofs <= 252 && !(ofs & 3) && !((rd ^ (ofs >>2)) & 1) &&
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as->mcp != as->mcloop) {
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as->mcp++;
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emit_lsox(as, ai == ARMI_LDR ? ARMI_LDRD : ARMI_STRD, rd&~1, rn, ofs&~4);
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return;
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}
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if (ofs < 0) ofs = -ofs; else ai |= ARMI_LS_U;
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*--as->mcp = ai | ARMI_LS_P | ARMF_D(rd) | ARMF_N(rn) | ofs;
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}
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/* -- Emit loads/stores --------------------------------------------------- */
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/* Prefer spills of BASE/L. */
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#define emit_canremat(ref) ((ref) < ASMREF_L)
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/* Try to find a one step delta relative to another constant. */
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static int emit_kdelta1(ASMState *as, Reg d, int32_t i)
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{
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RegSet work = ~as->freeset & RSET_GPR;
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while (work) {
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Reg r = rset_picktop(work);
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IRRef ref = regcost_ref(as->cost[r]);
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lua_assert(r != d);
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if (emit_canremat(ref)) {
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int32_t delta = i - (ra_iskref(ref) ? ra_krefk(as, ref) : IR(ref)->i);
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uint32_t k = emit_isk12(ARMI_ADD, delta);
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if (k) {
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if (k == ARMI_K12)
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emit_dm(as, ARMI_MOV, d, r);
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else
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emit_dn(as, ARMI_ADD^k, d, r);
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return 1;
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}
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}
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rset_clear(work, r);
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}
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return 0; /* Failed. */
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}
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/* Try to find a two step delta relative to another constant. */
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static int emit_kdelta2(ASMState *as, Reg d, int32_t i)
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{
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RegSet work = ~as->freeset & RSET_GPR;
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while (work) {
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Reg r = rset_picktop(work);
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IRRef ref = regcost_ref(as->cost[r]);
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lua_assert(r != d);
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if (emit_canremat(ref)) {
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int32_t delta = i - (ra_iskref(ref) ? ra_krefk(as, ref) : IR(ref)->i);
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uint32_t sh, inv = 0, k2, k;
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if (delta < 0) { delta = -delta; inv = ARMI_ADD^ARMI_SUB; }
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sh = lj_ffs(delta) & ~1;
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k2 = emit_isk12(0, delta & (255 << sh));
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k = emit_isk12(0, delta & ~(255 << sh));
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if (k) {
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emit_dn(as, ARMI_ADD^k2^inv, d, d);
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emit_dn(as, ARMI_ADD^k^inv, d, r);
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return 1;
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}
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}
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rset_clear(work, r);
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}
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return 0; /* Failed. */
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}
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/* Load a 32 bit constant into a GPR. */
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static void emit_loadi(ASMState *as, Reg r, int32_t i)
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{
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uint32_t k = emit_isk12(ARMI_MOV, i);
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lua_assert(rset_test(as->freeset, r) || r == RID_TMP);
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if (k) {
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/* Standard K12 constant. */
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emit_d(as, ARMI_MOV^k, r);
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} else if ((as->flags & JIT_F_ARMV6T2) && (uint32_t)i < 0x00010000u) {
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/* 16 bit loword constant for ARMv6T2. */
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emit_d(as, ARMI_MOVW|(i & 0x0fff)|((i & 0xf000)<<4), r);
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} else if (emit_kdelta1(as, r, i)) {
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/* One step delta relative to another constant. */
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} else if ((as->flags & JIT_F_ARMV6T2)) {
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/* 32 bit hiword/loword constant for ARMv6T2. */
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emit_d(as, ARMI_MOVT|((i>>16) & 0x0fff)|(((i>>16) & 0xf000)<<4), r);
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emit_d(as, ARMI_MOVW|(i & 0x0fff)|((i & 0xf000)<<4), r);
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} else if (emit_kdelta2(as, r, i)) {
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/* Two step delta relative to another constant. */
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} else {
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/* Otherwise construct the constant with up to 4 instructions. */
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/* NYI: use mvn+bic, use pc-relative loads. */
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for (;;) {
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uint32_t sh = lj_ffs(i) & ~1;
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int32_t m = i & (255 << sh);
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i &= ~(255 << sh);
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if (i == 0) {
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emit_d(as, ARMI_MOV ^ emit_isk12(0, m), r);
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break;
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}
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emit_dn(as, ARMI_ORR ^ emit_isk12(0, m), r, r);
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}
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}
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}
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#define emit_loada(as, r, addr) emit_loadi(as, (r), i32ptr((addr)))
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static Reg ra_allock(ASMState *as, int32_t k, RegSet allow);
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/* Get/set from constant pointer. */
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static void emit_lsptr(ASMState *as, ARMIns ai, Reg r, void *p)
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{
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int32_t i = i32ptr(p);
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emit_lso(as, ai, r, ra_allock(as, (i & ~4095), rset_exclude(RSET_GPR, r)),
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(i & 4095));
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}
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/* Get/set global_State fields. */
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#define emit_getgl(as, r, field) \
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emit_lsptr(as, ARMI_LDR, (r), (void *)&J2G(as->J)->field)
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#define emit_setgl(as, r, field) \
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emit_lsptr(as, ARMI_STR, (r), (void *)&J2G(as->J)->field)
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/* Trace number is determined from pc of exit instruction. */
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#define emit_setvmstate(as, i) UNUSED(i)
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/* -- Emit control-flow instructions -------------------------------------- */
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/* Label for internal jumps. */
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typedef MCode *MCLabel;
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/* Return label pointing to current PC. */
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#define emit_label(as) ((as)->mcp)
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static void emit_branch(ASMState *as, ARMIns ai, MCode *target)
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{
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MCode *p = as->mcp;
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ptrdiff_t delta = (target - p) - 1;
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lua_assert(((delta + 0x00800000) >> 24) == 0);
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*--p = ai | ((uint32_t)delta & 0x00ffffffu);
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as->mcp = p;
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}
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static void emit_call(ASMState *as, void *target)
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{
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MCode *p = --as->mcp;
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ptrdiff_t delta = ((char *)target - (char *)p) - 8;
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if ((((delta>>2) + 0x00800000) >> 24) == 0) {
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if ((delta & 1))
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*p = ARMI_BLX | ((uint32_t)(delta>>2) & 0x00ffffffu) | ((delta&2) << 27);
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else
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*p = ARMI_BL | ((uint32_t)(delta>>2) & 0x00ffffffu);
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} else { /* Target out of range: need indirect call. But don't use R0-R3. */
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Reg r = ra_allock(as, i32ptr(target), RSET_RANGE(RID_R4, RID_R12+1));
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*p = ARMI_BLXr | ARMF_M(r);
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}
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}
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/* -- Emit generic operations --------------------------------------------- */
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/* Generic move between two regs. */
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static void emit_movrr(ASMState *as, IRIns *ir, Reg dst, Reg src)
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{
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lua_assert(!irt_isnum(ir->t)); UNUSED(ir);
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if (as->mcp != as->mcloop) { /* Swap early registers for loads/stores. */
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MCode ins = *as->mcp, swp = (src^dst);
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if ((ins & 0x0c000000) == 0x04000000 && (ins & 0x02000010) != 0x02000010) {
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if (!((ins ^ (dst << 16)) & 0x000f0000))
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*as->mcp = ins ^ (swp << 16); /* Swap N in load/store. */
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if (!(ins & 0x00100000) && !((ins ^ (dst << 12)) & 0x0000f000))
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*as->mcp = ins ^ (swp << 12); /* Swap D in store. */
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}
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}
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emit_dm(as, ARMI_MOV, dst, src);
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}
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/* Generic load of register from stack slot. */
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static void emit_spload(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
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{
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lua_assert(!irt_isnum(ir->t)); UNUSED(ir);
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emit_lso(as, ARMI_LDR, r, RID_SP, ofs);
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}
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/* Generic store of register to stack slot. */
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static void emit_spstore(ASMState *as, IRIns *ir, Reg r, int32_t ofs)
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{
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lua_assert(!irt_isnum(ir->t)); UNUSED(ir);
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emit_lso(as, ARMI_STR, r, RID_SP, ofs);
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}
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/* Emit an arithmetic/logic operation with a constant operand. */
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static void emit_opk(ASMState *as, ARMIns ai, Reg dest, Reg src,
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int32_t i, RegSet allow)
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{
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uint32_t k = emit_isk12(ai, i);
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if (k)
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emit_dn(as, ai^k, dest, src);
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else
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emit_dnm(as, ai, dest, src, ra_allock(as, i, allow));
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}
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/* Add offset to pointer. */
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static void emit_addptr(ASMState *as, Reg r, int32_t ofs)
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{
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if (ofs)
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emit_opk(as, ARMI_ADD, r, r, ofs, rset_exclude(RSET_GPR, r));
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}
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#define emit_spsub(as, ofs) emit_addptr(as, RID_SP, -(ofs))
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@ -125,6 +125,8 @@ typedef uint32_t RegCost;
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#if LJ_TARGET_X86ORX64
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#include "lj_target_x86.h"
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#elif LJ_TARGET_ARM
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#include "lj_target_arm.h"
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#else
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#error "Missing include for target CPU"
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#endif
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205
src/lj_target_arm.h
Normal file
205
src/lj_target_arm.h
Normal file
@ -0,0 +1,205 @@
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/*
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** Definitions for ARM CPUs.
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** Copyright (C) 2005-2011 Mike Pall. See Copyright Notice in luajit.h
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*/
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#ifndef _LJ_TARGET_ARM_H
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#define _LJ_TARGET_ARM_H
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/* -- Registers IDs ------------------------------------------------------- */
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#define GPRDEF(_) \
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_(R0) _(R1) _(R2) _(R3) _(R4) _(R5) _(R6) _(R7) \
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_(R8) _(R9) _(R10) _(R11) _(R12) _(SP) _(LR) _(PC)
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#if LJ_SOFTFP
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#define FPRDEF(_)
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#else
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#error "NYI: hard-float support for ARM"
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#endif
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#define VRIDDEF(_)
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#define RIDENUM(name) RID_##name,
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enum {
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GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
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FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
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RID_MAX,
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RID_TMP = RID_LR,
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/* Calling conventions. */
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RID_RET = RID_R0,
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RID_RETHI = RID_R1,
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RID_FPRET = RID_R0,
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/* These definitions must match with the *.dasc file(s): */
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RID_BASE = RID_R9, /* Interpreter BASE. */
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RID_LPC = RID_R6, /* Interpreter PC. */
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RID_DISPATCH = RID_R7, /* Interpreter DISPATCH table. */
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RID_LREG = RID_R8, /* Interpreter L. */
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/* Register ranges [min, max) and number of registers. */
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RID_MIN_GPR = RID_R0,
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RID_MAX_GPR = RID_PC+1,
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RID_MIN_FPR = RID_MAX_GPR,
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#if LJ_SOFTFP
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RID_MAX_FPR = RID_MIN_FPR,
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#else
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#error "NYI: VFP support for ARM"
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#endif
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RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
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RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR
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};
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#define RID_NUM_KREF RID_NUM_GPR
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#define RID_MIN_KREF RID_R0
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/* -- Register sets ------------------------------------------------------- */
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/* Make use of all registers, except sp, lr and pc. */
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#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_R12+1))
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#define RSET_GPREVEN \
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(RID2RSET(RID_R0)|RID2RSET(RID_R2)|RID2RSET(RID_R4)|RID2RSET(RID_R6)| \
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RID2RSET(RID_R8)|RID2RSET(RID_R10))
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#define RSET_GPRODD \
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(RID2RSET(RID_R1)|RID2RSET(RID_R3)|RID2RSET(RID_R5)|RID2RSET(RID_R7)| \
|
||||
RID2RSET(RID_R9)|RID2RSET(RID_R11))
|
||||
#if LJ_SOFTFP
|
||||
#define RSET_FPR 0
|
||||
#define RSET_ALL RSET_GPR
|
||||
#else
|
||||
#error "NYI: VFP support for ARM"
|
||||
#endif
|
||||
#define RSET_INIT RSET_ALL
|
||||
|
||||
/* ABI-specific register sets. lr is an implicit scratch register. */
|
||||
#define RSET_SCRATCH_GPR_ (RSET_RANGE(RID_R0, RID_R3+1)|RID2RSET(RID_R12))
|
||||
#ifdef __APPLE__
|
||||
#define RSET_SCRATCH_GPR (RSET_SCRATCH_GPR_|RID2RSET(RID_R9))
|
||||
#else
|
||||
#define RSET_SCRATCH_GPR RSET_SCRATCH_GPR_
|
||||
#endif
|
||||
#if LJ_SOFTFP
|
||||
#define RSET_SCRATCH_FPR 0
|
||||
#else
|
||||
#error "NYI: VFP support for ARM"
|
||||
#endif
|
||||
#define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
|
||||
#define REGARG_FIRSTGPR RID_R0
|
||||
#define REGARG_LASTGPR RID_R3
|
||||
#define REGARG_NUMGPR 4
|
||||
|
||||
/* -- Spill slots --------------------------------------------------------- */
|
||||
|
||||
/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
|
||||
**
|
||||
** SPS_FIXED: Available fixed spill slots in interpreter frame.
|
||||
** This definition must match with the *.dasc file(s).
|
||||
**
|
||||
** SPS_FIRST: First spill slot for general use. Reserve min. two 32 bit slots.
|
||||
*/
|
||||
#define SPS_FIXED 2
|
||||
#define SPS_FIRST 2
|
||||
|
||||
#define sps_scale(slot) (4 * (int32_t)(slot))
|
||||
#define sps_align(slot) (((slot) - SPS_FIXED + 1) & ~1)
|
||||
|
||||
/* -- Exit state ---------------------------------------------------------- */
|
||||
|
||||
/* This definition must match with the *.dasc file(s). */
|
||||
typedef struct {
|
||||
#if !LJ_SOFTFP
|
||||
lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
|
||||
#endif
|
||||
int32_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
|
||||
int32_t spill[256]; /* Spill slots. */
|
||||
} ExitState;
|
||||
|
||||
/* PC after instruction that caused an exit. Used to find the trace number. */
|
||||
#define EXITSTATE_PCREG RID_PC
|
||||
|
||||
#define EXITSTUB_SPACING 4
|
||||
#define EXITSTUBS_PER_GROUP 32
|
||||
|
||||
/* -- Instructions -------------------------------------------------------- */
|
||||
|
||||
/* Instruction fields. */
|
||||
#define ARMF_CC(ai, cc) (((ai) ^ ARMI_CCAL) | ((cc) << 28))
|
||||
#define ARMF_N(r) ((r) << 16)
|
||||
#define ARMF_D(r) ((r) << 12)
|
||||
#define ARMF_S(r) ((r) << 8)
|
||||
#define ARMF_M(r) (r)
|
||||
#define ARMF_SH(sh, n) (((sh) << 5) | ((n) << 7))
|
||||
#define ARMF_RSH(sh, r) (0x10 | ((sh) << 5) | ARMF_S(r))
|
||||
|
||||
typedef enum ARMIns {
|
||||
ARMI_CCAL = 0xe0000000,
|
||||
ARMI_S = 0x000100000,
|
||||
ARMI_K12 = 0x02000000,
|
||||
ARMI_KNEG = 0x00200000,
|
||||
ARMI_LS_U = 0x00800000,
|
||||
ARMI_LS_P = 0x01000000,
|
||||
ARMI_LS_R = 0x02000000,
|
||||
ARMI_LSX_I = 0x00400000,
|
||||
|
||||
ARMI_AND = 0xe0000000,
|
||||
ARMI_EOR = 0xe0200000,
|
||||
ARMI_SUB = 0xe0400000,
|
||||
ARMI_RSB = 0xe0600000,
|
||||
ARMI_ADD = 0xe0800000,
|
||||
ARMI_ADC = 0xe0a00000,
|
||||
ARMI_SBC = 0xe0c00000,
|
||||
ARMI_RSC = 0xe0e00000,
|
||||
ARMI_TST = 0xe1100000,
|
||||
ARMI_TEQ = 0xe1300000,
|
||||
ARMI_CMP = 0xe1500000,
|
||||
ARMI_CMN = 0xe1700000,
|
||||
ARMI_ORR = 0xe1800000,
|
||||
ARMI_MOV = 0xe1a00000,
|
||||
ARMI_BIC = 0xe1c00000,
|
||||
ARMI_MVN = 0xe1e00000,
|
||||
|
||||
ARMI_NOP = 0xe1a00000,
|
||||
|
||||
ARMI_MUL = 0xe0000090,
|
||||
ARMI_SMULL = 0xe0c00090,
|
||||
|
||||
ARMI_LDR = 0xe4100000,
|
||||
ARMI_LDRB = 0xe4500000,
|
||||
ARMI_LDRH = 0xe01000b0,
|
||||
ARMI_LDRSB = 0xe01000d0,
|
||||
ARMI_LDRSH = 0xe01000f0,
|
||||
ARMI_LDRD = 0xe00000d0,
|
||||
ARMI_STR = 0xe4000000,
|
||||
ARMI_STRB = 0xe4400000,
|
||||
ARMI_STRH = 0xe00000b0,
|
||||
ARMI_STRD = 0xe00000f0,
|
||||
|
||||
ARMI_B = 0xea000000,
|
||||
ARMI_BL = 0xeb000000,
|
||||
ARMI_BLX = 0xfa000000,
|
||||
ARMI_BLXr = 0xe12fff30,
|
||||
|
||||
/* ARMv6 */
|
||||
ARMI_REV = 0xe6bf0f30,
|
||||
ARMI_SXTB = 0xe6af0070,
|
||||
ARMI_SXTH = 0xe6bf0070,
|
||||
ARMI_UXTB = 0xe6ef0070,
|
||||
ARMI_UXTH = 0xe6ff0070,
|
||||
|
||||
/* ARMv6T2 */
|
||||
ARMI_MOVW = 0xe3000000,
|
||||
ARMI_MOVT = 0xe3400000,
|
||||
} ARMIns;
|
||||
|
||||
typedef enum ARMShift {
|
||||
ARMSH_LSL, ARMSH_LSR, ARMSH_ASR, ARMSH_ROR
|
||||
} ARMShift;
|
||||
|
||||
/* ARM condition codes. */
|
||||
typedef enum ARMCC {
|
||||
CC_EQ, CC_NE, CC_CS, CC_CC, CC_MI, CC_PL, CC_VS, CC_VC,
|
||||
CC_HI, CC_LS, CC_GE, CC_LT, CC_GT, CC_LE, CC_AL,
|
||||
CC_HS = CC_CS, CC_LO = CC_CC
|
||||
} ARMCC;
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user