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Update vm_s390x.dasc
made some changes like mentioning arch from x86 to S390x removed some x86 specific code
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@ -1,12 +1,9 @@
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|// Low-level VM code for x86 CPUs.
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|// Low-level VM code for S390x CPUs.
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|// Bytecode interpreter, fast functions and helper functions.
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|// Copyright (C) 2005-2016 Mike Pall. See Copyright Notice in luajit.h
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|
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|.if P64
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|.arch x64
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|.else
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|.arch x86
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|.endif
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|.arch S390x
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|.section code_op, code_sub
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|.actionlist build_actionlist
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@ -16,13 +13,6 @@
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|//-----------------------------------------------------------------------
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|.if P64
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|.define X64, 1
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|.if WIN
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|.define X64WIN, 1
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|.endif
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|.endif
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|// Fixed register assignments for the interpreter.
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|// This is very fragile and has many dependencies. Caveat emptor.
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|.define BASE, edx // Not C callee-save, refetched anyway.
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@ -119,10 +109,6 @@
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|// Stack layout while in interpreter. Must match with lj_frame.h.
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|//-----------------------------------------------------------------------
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|.if not X64 // x86 stack layout.
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|.if WIN
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|.define CFRAME_SPACE, aword*9 // Delta for esp (see <--).
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|.macro saveregs_
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| push edi; push esi; push ebx
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@ -138,51 +124,9 @@
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| pop ebx; pop esi; pop edi; pop ebp
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|.endmacro
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|.else
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|.define CFRAME_SPACE, aword*7 // Delta for esp (see <--).
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|.macro saveregs_
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| push edi; push esi; push ebx
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| sub esp, CFRAME_SPACE
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|.endmacro
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|.macro restoreregs
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| add esp, CFRAME_SPACE
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| pop ebx; pop esi; pop edi; pop ebp
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|.endmacro
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|.endif
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|.macro saveregs
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| push ebp; saveregs_
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|.endmacro
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|.if WIN
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|.define SAVE_ERRF, aword [esp+aword*19] // vm_pcall/vm_cpcall only.
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|.define SAVE_NRES, aword [esp+aword*18]
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|.define SAVE_CFRAME, aword [esp+aword*17]
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|.define SAVE_L, aword [esp+aword*16]
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|//----- 16 byte aligned, ^^^ arguments from C caller
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|.define SAVE_RET, aword [esp+aword*15] //<-- esp entering interpreter.
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|.define SAVE_R4, aword [esp+aword*14]
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|.define SAVE_R3, aword [esp+aword*13]
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|.define SAVE_R2, aword [esp+aword*12]
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|//----- 16 byte aligned
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|.define SAVE_R1, aword [esp+aword*11]
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|.define SEH_FUNC, aword [esp+aword*10]
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|.define SEH_NEXT, aword [esp+aword*9] //<-- esp after register saves.
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|.define UNUSED2, aword [esp+aword*8]
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|//----- 16 byte aligned
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|.define UNUSED1, aword [esp+aword*7]
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|.define SAVE_PC, aword [esp+aword*6]
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|.define TMP2, aword [esp+aword*5]
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|.define TMP1, aword [esp+aword*4]
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|//----- 16 byte aligned
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|.define ARG4, aword [esp+aword*3]
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|.define ARG3, aword [esp+aword*2]
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|.define ARG2, aword [esp+aword*1]
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|.define ARG1, aword [esp] //<-- esp while in interpreter.
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|//----- 16 byte aligned, ^^^ arguments for C callee
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|.else
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|.define SAVE_ERRF, aword [esp+aword*15] // vm_pcall/vm_cpcall only.
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|.define SAVE_NRES, aword [esp+aword*14]
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|.define SAVE_CFRAME, aword [esp+aword*13]
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@ -203,7 +147,6 @@
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|.define ARG2, aword [esp+aword*1]
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|.define ARG1, aword [esp] //<-- esp while in interpreter.
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|//----- 16 byte aligned, ^^^ arguments for C callee
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|.endif
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|// FPARGx overlaps ARGx and ARG(x+1) on x86.
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|.define FPARG3, qword [esp+qword*1]
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@ -215,112 +158,6 @@
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|.define TMPa, TMP1
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|.define MULTRES, TMP2
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|// Arguments for vm_call and vm_pcall.
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|.define INARG_BASE, SAVE_CFRAME // Overwritten by SAVE_CFRAME!
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|// Arguments for vm_cpcall.
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|.define INARG_CP_CALL, SAVE_ERRF
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|.define INARG_CP_UD, SAVE_NRES
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|.define INARG_CP_FUNC, SAVE_CFRAME
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|//-----------------------------------------------------------------------
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|.elif X64WIN // x64/Windows stack layout
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|.define CFRAME_SPACE, aword*5 // Delta for rsp (see <--).
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|.macro saveregs_
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| push rdi; push rsi; push rbx
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| sub rsp, CFRAME_SPACE
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|.endmacro
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|.macro saveregs
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| push rbp; saveregs_
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|.endmacro
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|.macro restoreregs
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| add rsp, CFRAME_SPACE
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| pop rbx; pop rsi; pop rdi; pop rbp
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|.endmacro
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|.define SAVE_CFRAME, aword [rsp+aword*13]
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|.define SAVE_PC, dword [rsp+dword*25]
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|.define SAVE_L, dword [rsp+dword*24]
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|.define SAVE_ERRF, dword [rsp+dword*23]
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|.define SAVE_NRES, dword [rsp+dword*22]
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|.define TMP2, dword [rsp+dword*21]
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|.define TMP1, dword [rsp+dword*20]
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|//----- 16 byte aligned, ^^^ 32 byte register save area, owned by interpreter
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|.define SAVE_RET, aword [rsp+aword*9] //<-- rsp entering interpreter.
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|.define SAVE_R4, aword [rsp+aword*8]
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|.define SAVE_R3, aword [rsp+aword*7]
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|.define SAVE_R2, aword [rsp+aword*6]
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|.define SAVE_R1, aword [rsp+aword*5] //<-- rsp after register saves.
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|.define ARG5, aword [rsp+aword*4]
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|.define CSAVE_4, aword [rsp+aword*3]
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|.define CSAVE_3, aword [rsp+aword*2]
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|.define CSAVE_2, aword [rsp+aword*1]
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|.define CSAVE_1, aword [rsp] //<-- rsp while in interpreter.
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|//----- 16 byte aligned, ^^^ 32 byte register save area, owned by callee
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|// TMPQ overlaps TMP1/TMP2. MULTRES overlaps TMP2 (and TMPQ).
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|.define TMPQ, qword [rsp+aword*10]
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|.define MULTRES, TMP2
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|.define TMPa, ARG5
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|.define ARG5d, dword [rsp+aword*4]
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|.define TMP3, ARG5d
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|//-----------------------------------------------------------------------
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|.else // x64/POSIX stack layout
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|.define CFRAME_SPACE, aword*5 // Delta for rsp (see <--).
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|.macro saveregs_
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| push rbx; push r15; push r14
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|.if NO_UNWIND
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| push r13; push r12
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|.endif
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| sub rsp, CFRAME_SPACE
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|.endmacro
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|.macro saveregs
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| push rbp; saveregs_
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|.endmacro
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|.macro restoreregs
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| add rsp, CFRAME_SPACE
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|.if NO_UNWIND
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| pop r12; pop r13
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|.endif
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| pop r14; pop r15; pop rbx; pop rbp
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|.endmacro
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|//----- 16 byte aligned,
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|.if NO_UNWIND
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|.define SAVE_RET, aword [rsp+aword*11] //<-- rsp entering interpreter.
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|.define SAVE_R4, aword [rsp+aword*10]
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|.define SAVE_R3, aword [rsp+aword*9]
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|.define SAVE_R2, aword [rsp+aword*8]
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|.define SAVE_R1, aword [rsp+aword*7]
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|.define SAVE_RU2, aword [rsp+aword*6]
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|.define SAVE_RU1, aword [rsp+aword*5] //<-- rsp after register saves.
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|.else
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|.define SAVE_RET, aword [rsp+aword*9] //<-- rsp entering interpreter.
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|.define SAVE_R4, aword [rsp+aword*8]
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|.define SAVE_R3, aword [rsp+aword*7]
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|.define SAVE_R2, aword [rsp+aword*6]
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|.define SAVE_R1, aword [rsp+aword*5] //<-- rsp after register saves.
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|.endif
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|.define SAVE_CFRAME, aword [rsp+aword*4]
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|.define SAVE_PC, dword [rsp+dword*7]
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|.define SAVE_L, dword [rsp+dword*6]
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|.define SAVE_ERRF, dword [rsp+dword*5]
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|.define SAVE_NRES, dword [rsp+dword*4]
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|.define TMPa, aword [rsp+aword*1]
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|.define TMP2, dword [rsp+dword*1]
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|.define TMP1, dword [rsp] //<-- rsp while in interpreter.
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|//----- 16 byte aligned
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|// TMPQ overlaps TMP1/TMP2. MULTRES overlaps TMP2 (and TMPQ).
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|.define TMPQ, qword [rsp]
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|.define TMP3, dword [rsp+aword*1]
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|.define MULTRES, TMP2
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|.endif
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|//-----------------------------------------------------------------------
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|// Instruction headers.
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@ -339,11 +176,6 @@
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| movzx OP, RCL
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| add PC, 4
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| shr RC, 16
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|.if X64
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| jmp aword [DISPATCH+OP*8]
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|.else
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| jmp aword [DISPATCH+OP*4]
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|.endif
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|.endmacro
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|
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|// Instruction footer.
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@ -433,30 +265,9 @@
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| mov dword [DISPATCH+DISPATCH_GL(vmstate)], ~LJ_VMST_..st
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|.endmacro
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|// x87 compares.
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|.macro fcomparepp // Compare and pop st0 >< st1.
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| fucomip st1
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| fpop
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|.endmacro
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|.macro fpop1; fstp st1; .endmacro
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|
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|// Synthesize SSE FP constants.
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|.macro sseconst_abs, reg, tmp // Synthesize abs mask.
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|.if X64
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| mov64 tmp, U64x(7fffffff,ffffffff); movd reg, tmp
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|.else
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| pxor reg, reg; pcmpeqd reg, reg; psrlq reg, 1
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|.endif
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|.endmacro
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|.macro sseconst_hi, reg, tmp, val // Synthesize hi-32 bit const.
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|.if X64
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| mov64 tmp, U64x(val,00000000); movd reg, tmp
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|.else
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| mov tmp, 0x .. val; movd reg, tmp; pshufd reg, reg, 0x51
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|.endif
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|.endmacro
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|.macro sseconst_sign, reg, tmp // Synthesize sign mask.
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| sseconst_hi reg, tmp, 80000000
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