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Fix store opcodes with dynamic destructive out register not being correctly allocated an input register

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This commit is contained in:
fsfod 2016-03-29 12:15:55 +01:00
parent 748091cfd9
commit 4eaf7f6efe
3 changed files with 3 additions and 3 deletions
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2
src/lj_asm.c
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@ -2743,7 +2743,7 @@ static void wrap_intrins(jit_State *J, CIntrinsic *intrins, IntrinWrapState *sta
/* Allocate the dynamic output register */ /* Allocate the dynamic output register */
if (intrins->outsz > 0 && intrin_dynrout(intrins)) { if (intrins->outsz > 0 && intrin_dynrout(intrins)) {
if (dynreg == DYNREG_INOUT) { if (dynreg == DYNREG_INOUT || dynreg == DYNREG_TWOSTORE) {
rout = reg_rid(in[1]); rout = reg_rid(in[1]);
out[0] = reg_setrid(out[0], rout); out[0] = reg_setrid(out[0], rout);
} else if (dynreg == DYNREG_OPEXT) { } else if (dynreg == DYNREG_OPEXT) {

2
src/lj_asm_x86.h
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@ -868,7 +868,7 @@ static void asm_intrin_opcode(ASMState *as, IRIns *ir, IntrinsInfo *ininfo)
lua_assert(ra_hasreg(right) && (ra_hasreg(dest) || intrins->dyninsz < 2)); lua_assert(ra_hasreg(right) && (ra_hasreg(dest) || intrins->dyninsz < 2));
emit_intrins(as, intrins, right, dest, vvvv); emit_intrins(as, intrins, right, dest, vvvv);
if (dynreg == DYNREG_INOUT) { if (dynreg == DYNREG_INOUT || (dynreg == DYNREG_TWOSTORE && dynrout)) {
lua_assert(lref); lua_assert(lref);
ra_left(as, dest, lref); ra_left(as, dest, lref);
/* no need to load the register since ra_left already did */ /* no need to load the register since ra_left already did */

2
src/lj_intrinsic.h
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@ -28,7 +28,7 @@ typedef enum REGMODE {
DYNREG_ONE, DYNREG_ONE,
/* 1(R) register in, 1 out(M) which can be a memory address to store the value */ /* 1(R) register in, 1 out(M) which can be a memory address to store the value */
DYNREG_ONESTORE, DYNREG_ONESTORE,
/* 2 in 0 out first must always be treated as indirect */ /* 2 in with R optionally being destructive out. first must always be treated as indirect */
DYNREG_TWOSTORE, DYNREG_TWOSTORE,
/* one input(M) register and the second is part of part of the opcode */ /* one input(M) register and the second is part of part of the opcode */
DYNREG_OPEXT, DYNREG_OPEXT,