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https://github.com/LuaJIT/LuaJIT.git
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Add x64 call argument setup. More 32/64 bit cleanups in assembler.
This commit is contained in:
Mike Pall
parent
b95294572c
commit
3c6cec0846
100
src/lj_asm.c
100
src/lj_asm.c
@ -1292,21 +1292,52 @@ static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
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{
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RegSet allow = RSET_ALL;
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uint32_t n, nargs = CCI_NARGS(ci);
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int32_t ofs = 0;
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int32_t ofs = STACKARG_OFS;
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uint32_t gprs = REGARG_GPRS;
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#if LJ_64
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Reg fpr = REGARG_FIRSTFPR;
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#endif
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lua_assert(!(nargs > 2 && (ci->flags&CCI_FASTCALL))); /* Avoid stack adj. */
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emit_call(as, ci->func);
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for (n = 0; n < nargs; n++) { /* Setup args. */
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#if LJ_64
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#error "NYI: 64 bit mode call argument setup"
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#endif
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IRIns *ir = IR(args[n]);
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Reg r;
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#if LJ_64 && defined(_WIN64)
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/* Windows/x64 argument registers are strictly positional. */
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r = irt_isnum(ir->t) ? (fpr <= REGARG_LASTFPR ? fpr : 0) : (gprs & 31);
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fpr++; gprs >>= 5;
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#elif LJ_64
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/* POSIX/x64 argument registers are used in order of appearance. */
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if (irt_isnum(ir->t)) {
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if ((ofs & 4) && irref_isk(args[n])) {
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r = fpr <= REGARG_LASTFPR ? fpr : 0; fpr++;
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} else {
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r = gprs & 31; gprs >>= 5;
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}
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#else
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if (irt_isnum(ir->t) || !(ci->flags & CCI_FASTCALL)) {
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r = 0;
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} else {
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r = gprs & 31; gprs >>= 5;
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}
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#endif
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if (r) { /* Argument is in a register. */
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if (args[n] < ASMREF_TMP1) {
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emit_loadi(as, r, ir->i);
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} else {
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lua_assert(rset_test(as->freeset, r)); /* Must have been evicted. */
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if (ra_hasreg(ir->r)) {
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ra_noweak(as, ir->r);
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ra_movrr(as, ir, r, ir->r);
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} else {
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ra_allocref(as, args[n], RID2RSET(r));
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}
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}
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} else if (irt_isnum(ir->t)) { /* FP argument is on stack. */
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if (!LJ_64 && (ofs & 4) && irref_isk(args[n])) {
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/* Split stores for unaligned FP consts. */
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emit_movmroi(as, RID_ESP, ofs, (int32_t)ir_knum(ir)->u32.lo);
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emit_movmroi(as, RID_ESP, ofs+4, (int32_t)ir_knum(ir)->u32.hi);
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} else {
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Reg r;
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if ((allow & RSET_FPR) == RSET_EMPTY)
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lj_trace_err(as->J, LJ_TRERR_NYICOAL);
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r = ra_alloc1(as, args[n], allow & RSET_FPR);
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@ -1314,34 +1345,18 @@ static void asm_gencall(ASMState *as, const CCallInfo *ci, IRRef *args)
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emit_rmro(as, XO_MOVSDto, r, RID_ESP, ofs);
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}
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ofs += 8;
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} else {
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if ((ci->flags & CCI_FASTCALL) && n < 2) {
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Reg r = n == 0 ? RID_ECX : RID_EDX;
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if (args[n] < ASMREF_TMP1) {
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emit_loadi(as, r, ir->i);
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} else {
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lua_assert(rset_test(as->freeset, r)); /* Must have been evicted. */
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allow &= ~RID2RSET(r);
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if (ra_hasreg(ir->r)) {
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ra_noweak(as, ir->r);
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ra_movrr(as, ir, r, ir->r);
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} else {
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ra_allocref(as, args[n], RID2RSET(r));
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}
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}
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} else { /* Non-FP argument is on stack. */
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/* NYI: no widening for 64 bit parameters on x64. */
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if (args[n] < ASMREF_TMP1) {
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emit_movmroi(as, RID_ESP, ofs, ir->i);
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} else {
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if (args[n] < ASMREF_TMP1) {
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emit_movmroi(as, RID_ESP, ofs, ir->i);
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} else {
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Reg r;
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if ((allow & RSET_GPR) == RSET_EMPTY)
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lj_trace_err(as->J, LJ_TRERR_NYICOAL);
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r = ra_alloc1(as, args[n], allow & RSET_GPR);
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allow &= ~RID2RSET(r);
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emit_movtomro(as, r, RID_ESP, ofs);
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}
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ofs += 4;
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if ((allow & RSET_GPR) == RSET_EMPTY)
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lj_trace_err(as->J, LJ_TRERR_NYICOAL);
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r = ra_alloc1(as, args[n], allow & RSET_GPR);
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allow &= ~RID2RSET(r);
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emit_movtomro(as, REX_64LU(ir, r), RID_ESP, ofs);
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}
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ofs += sizeof(intptr_t);
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}
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}
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}
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@ -2561,7 +2576,7 @@ static void asm_comp_(ASMState *as, IRIns *ir, int cc)
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asm_guardcc(as, cc);
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if (usetest && left != RID_MRM) {
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/* Use test r,r instead of cmp r,0. */
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emit_rr(as, XO_TEST, left, left);
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emit_rr(as, XO_TEST, REX_64LU(ir, left), left);
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if (irl+1 == ir) /* Referencing previous ins? */
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as->testmcp = as->mcp; /* Set flag to drop test r,r if possible. */
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} else {
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@ -2580,11 +2595,7 @@ static void asm_comp_(ASMState *as, IRIns *ir, int cc)
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Reg left = ra_alloc1(as, lref, RSET_GPR);
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Reg right = asm_fuseload(as, rref, rset_exclude(RSET_GPR, left));
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asm_guardcc(as, cc);
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#if LJ_64
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if (irt_islightud(ir->t))
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left |= REX_64;
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#endif
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emit_mrm(as, XO_CMP, left, right);
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emit_mrm(as, XO_CMP, REX_64LU(ir, left), right);
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}
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}
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}
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@ -2732,14 +2743,14 @@ static void asm_gc_check(ASMState *as, SnapShot *snap)
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/* We don't know spadj yet, so get the C frame from L->cframe. */
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emit_movmroi(as, tmp, CFRAME_OFS_PC,
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(int32_t)as->T->snapmap[snap->mapofs+snap->nent]);
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emit_gri(as, XG_ARITHi(XOg_AND), tmp, CFRAME_RAWMASK);
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emit_gri(as, XG_ARITHi(XOg_AND), tmp|REX_64, CFRAME_RAWMASK);
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lstate = IR(ASMREF_L)->r;
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emit_rmro(as, XO_MOV, tmp, lstate, offsetof(lua_State, cframe));
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emit_rmro(as, XO_MOV, tmp|REX_64, lstate, offsetof(lua_State, cframe));
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/* It's ok if lstate is already in a non-scratch reg. But all allocations
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** in the non-fast path must use a scratch reg. See comment above.
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*/
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base = ra_alloc1(as, REF_BASE, rset_exclude(RSET_SCRATCH & RSET_GPR, lstate));
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emit_movtomro(as, base, lstate, offsetof(lua_State, base));
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emit_movtomro(as, base|REX_64, lstate, offsetof(lua_State, base));
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asm_gc_sync(as, snap, base);
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/* BASE/L get restored anyway, better do it inside the slow path. */
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if (as->parent || as->curins == as->loopref) ra_restore(as, REF_BASE);
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@ -3447,7 +3458,12 @@ static void asm_setup_regsp(ASMState *as, Trace *T)
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case IR_CALLN: case IR_CALLL: case IR_CALLS: {
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const CCallInfo *ci = &lj_ir_callinfo[ir->op2];
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#if LJ_64
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/* NYI: add stack slots for calls with more than 4/6 args. */
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/* NYI: add stack slots for x64 calls with many args. */
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#ifdef _WIN64
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lua_assert(CCI_NARGS(ci) <= 4);
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#else
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lua_assert(CCI_NARGS(ci) <= 6); /* Safe lower bound. */
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#endif
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ir->prev = REGSP_HINT(irt_isnum(ir->t) ? RID_FPRET : RID_RET);
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#else
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/* NYI: not fastcall-aware, but doesn't matter (yet). */
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@ -78,14 +78,27 @@ enum {
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/* Windows x64 ABI. */
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#define RSET_SCRATCH \
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(RSET_ACD|RSET_RANGE(RID_R8D, RID_R11D+1)|RSET_RANGE(RID_XMM0, RID_XMM5+1))
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#define REGARG_GPRS \
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(RID_ECX|((RID_EDX|((RID_R8D|(RID_R9D<<5))<<5))<<5))
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#define REGARG_FIRSTFPR RID_XMM0
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#define REGARG_LASTFPR RID_XMM3
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#define STACKARG_OFS (4*8)
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#else
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/* The rest of the civilized x64 world has a common ABI. */
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#define RSET_SCRATCH \
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(RSET_ACD|RSET_RANGE(RID_ESI, RID_R11D+1)|RSET_FPR)
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#define REGARG_GPRS \
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(RID_EDI|((RID_ESI|((RID_EDX|((RID_ECX|((RID_R8D|(RID_R9D \
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<<5))<<5))<<5))<<5))<<5))
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#define REGARG_FIRSTFPR RID_XMM0
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#define REGARG_LASTFPR RID_XMM7
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#define STACKARG_OFS 0
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#endif
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#else
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/* Common x86 ABI. */
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#define RSET_SCRATCH (RSET_ACD|RSET_FPR)
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#define REGARG_GPRS (RID_ECX|(RID_EDX<<5)) /* Fastcall only. */
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#define STACKARG_OFS 0
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#endif
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#if LJ_64
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@ -96,23 +109,26 @@ enum {
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/* -- Spill slots --------------------------------------------------------- */
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/* Available fixed spill slots in interpreter frame.
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/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
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**
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** SPS_FIXED: Available fixed spill slots in interpreter frame.
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** This definition must match with the *.dasc file(s).
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**
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** SPS_FIRST: First spill slot for general use. Reserve min. two 32 bit slots.
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*/
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#if LJ_64
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#ifdef _WIN64
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#define SPS_FIXED (5*2)
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#define SPS_FIRST (4*2) /* Don't use callee register save area. */
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#else
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#define SPS_FIXED 2
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#define SPS_FIRST 2
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#endif
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#else
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#define SPS_FIXED 6
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#define SPS_FIRST 2
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#endif
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/* First spill slot for general use. Reserve one 64 bit slot. */
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#define SPS_FIRST 2
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/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs. */
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#define sps_scale(slot) (4 * (int32_t)(slot))
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/* -- Exit state ---------------------------------------------------------- */
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