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riscv(support): add target definition
This commit is contained in:
gns
gns
parent
caeefe25d0
commit
33d45379ae
@ -55,7 +55,7 @@ typedef uint32_t RegSP;
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/* Bitset for registers. 32 registers suffice for most architectures.
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** Note that one set holds bits for both GPRs and FPRs.
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*/
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#if LJ_TARGET_PPC || LJ_TARGET_MIPS || LJ_TARGET_ARM64
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#if LJ_TARGET_PPC || LJ_TARGET_MIPS || LJ_TARGET_ARM64 || LJ_TARGET_RISCV64
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typedef uint64_t RegSet;
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#define RSET_BITS 6
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#define rset_picktop_(rs) ((Reg)lj_fls64(rs))
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@ -143,6 +143,8 @@ typedef uint32_t RegCost;
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#include "lj_target_ppc.h"
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#elif LJ_TARGET_MIPS
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#include "lj_target_mips.h"
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#elif LJ_TARGET_RISCV64
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#include "lj_target_riscv.h"
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#else
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#error "Missing include for target CPU"
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#endif
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542
src/lj_target_riscv.h
Normal file
542
src/lj_target_riscv.h
Normal file
@ -0,0 +1,542 @@
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/*
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** Definitions for RISC-V CPUs.
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** Copyright (C) 2005-2023 Mike Pall. See Copyright Notice in luajit.h
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*/
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#ifndef _LJ_TARGET_RISCV_H
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#define _LJ_TARGET_RISCV_H
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/* -- Registers IDs ------------------------------------------------------- */
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#define GPRDEF(_) \
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_(X0) _(RA) _(SP) _(X3) _(X4) _(X5) _(X6) _(X7) \
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_(X8) _(X9) _(X10) _(X11) _(X12) _(X13) _(X14) _(X15) \
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_(X16) _(X17) _(X18) _(X19) _(X20) _(X21) _(X22) _(X23) \
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_(X24) _(X25) _(X26) _(X27) _(X28) _(X29) _(X30) _(X31)
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#define FPRDEF(_) \
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_(F0) _(F1) _(F2) _(F3) _(F4) _(F5) _(F6) _(F7) \
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_(F8) _(F9) _(F10) _(F11) _(F12) _(F13) _(F14) _(F15) \
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_(F16) _(F17) _(F18) _(F19) _(F20) _(F21) _(F22) _(F23) \
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_(F24) _(F25) _(F26) _(F27) _(F28) _(F29) _(F30) _(F31)
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#define VRIDDEF(_)
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#define RIDENUM(name) RID_##name,
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enum {
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GPRDEF(RIDENUM) /* General-purpose registers (GPRs). */
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FPRDEF(RIDENUM) /* Floating-point registers (FPRs). */
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RID_MAX,
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RID_ZERO = RID_X0,
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RID_TMP = RID_RA,
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RID_GP = RID_X3,
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RID_TP = RID_X4,
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/* Calling conventions. */
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RID_RET = RID_X10,
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RID_RETLO = RID_X10,
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RID_RETHI = RID_X11,
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RID_FPRET = RID_F10,
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RID_CFUNCADDR = RID_X5,
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/* These definitions must match with the *.dasc file(s): */
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RID_BASE = RID_X18, /* Interpreter BASE. */
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RID_LPC = RID_X20, /* Interpreter PC. */
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RID_GL = RID_X21, /* Interpreter GL. */
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RID_LREG = RID_X23, /* Interpreter L. */
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/* Register ranges [min, max) and number of registers. */
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RID_MIN_GPR = RID_X0,
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RID_MAX_GPR = RID_X31+1,
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RID_MIN_FPR = RID_MAX_GPR,
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RID_MAX_FPR = RID_F31+1,
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RID_NUM_GPR = RID_MAX_GPR - RID_MIN_GPR,
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RID_NUM_FPR = RID_MAX_FPR - RID_MIN_FPR /* Only even regs are used. */
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};
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#define RID_NUM_KREF RID_NUM_GPR
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#define RID_MIN_KREF RID_X0
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/* -- Register sets ------------------------------------------------------- */
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/* Make use of all registers, except ZERO, TMP, SP, GP, TP, CFUNCADDR and GL. */
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#define RSET_FIXED \
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(RID2RSET(RID_ZERO)|RID2RSET(RID_TMP)|RID2RSET(RID_SP)|\
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RID2RSET(RID_GP)|RID2RSET(RID_TP)|RID2RSET(RID_GL))
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#define RSET_GPR (RSET_RANGE(RID_MIN_GPR, RID_MAX_GPR) - RSET_FIXED)
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#define RSET_FPR RSET_RANGE(RID_MIN_FPR, RID_MAX_FPR)
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#define RSET_ALL (RSET_GPR|RSET_FPR)
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#define RSET_INIT RSET_ALL
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#define RSET_SCRATCH_GPR \
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(RSET_RANGE(RID_X5, RID_X7+1)|RSET_RANGE(RID_X28, RID_X31+1)|\
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RSET_RANGE(RID_X10, RID_X17+1))
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#define RSET_SCRATCH_FPR \
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(RSET_RANGE(RID_F0, RID_F7+1)|RSET_RANGE(RID_F10, RID_F17+1)|\
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RSET_RANGE(RID_F28, RID_F31+1))
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#define RSET_SCRATCH (RSET_SCRATCH_GPR|RSET_SCRATCH_FPR)
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#define REGARG_FIRSTGPR RID_X10
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#define REGARG_LASTGPR RID_X17
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#define REGARG_NUMGPR 8
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#define REGARG_FIRSTFPR RID_F10
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#define REGARG_LASTFPR RID_F17
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#define REGARG_NUMFPR 8
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/* -- Spill slots --------------------------------------------------------- */
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/* Spill slots are 32 bit wide. An even/odd pair is used for FPRs.
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**
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** SPS_FIXED: Available fixed spill slots in interpreter frame.
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** This definition must match with the *.dasc file(s).
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**
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** SPS_FIRST: First spill slot for general use.
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*/
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#if LJ_32
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#define SPS_FIXED 5
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#else
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#define SPS_FIXED 4
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#endif
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#define SPS_FIRST 4
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#define SPOFS_TMP 0
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#define sps_scale(slot) (4 * (int32_t)(slot))
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#define sps_align(slot) (((slot) - SPS_FIXED + 3) & ~3)
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/* -- Exit state ---------------------------------------------------------- */
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/* This definition must match with the *.dasc file(s). */
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typedef struct {
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lua_Number fpr[RID_NUM_FPR]; /* Floating-point registers. */
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intptr_t gpr[RID_NUM_GPR]; /* General-purpose registers. */
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int32_t spill[256]; /* Spill slots. */
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} ExitState;
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/* Highest exit + 1 indicates stack check. */
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#define EXITSTATE_CHECKEXIT 1
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/* Return the address of a per-trace exit stub. */
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static LJ_AINLINE uint32_t *exitstub_trace_addr_(uint32_t *p, uint32_t exitno)
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{
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while (*p == 0x00000013) p++; /* Skip RISCVI_NOP. */
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return p + 4 + exitno;
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}
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/* Avoid dependence on lj_jit.h if only including lj_target.h. */
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#define exitstub_trace_addr(T, exitno) \
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exitstub_trace_addr_((MCode *)((char *)(T)->mcode + (T)->szmcode), (exitno))
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/* -- Instructions -------------------------------------------------------- */
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/* Instruction fields. */
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#define RISCVF_D(d) (((d)&31) << 7)
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#define RISCVF_S1(r) (((r)&31) << 15)
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#define RISCVF_S2(r) (((r)&31) << 20)
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#define RISCVF_S3(r) (((r)&31) << 27)
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#define RISCVF_FUNCT2(f) (((f)&3) << 25)
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#define RISCVF_FUNCT3(f) (((f)&7) << 12)
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#define RISCVF_FUNCT7(f) (((f)&127) << 25)
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#define RISCVF_SHAMT(s) ((s) << 20)
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#define RISCVF_RM(m) (((m)&7) << 12)
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#define RISCVF_IMMI(i) ((i) << 20)
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#define RISCVF_IMMS(i) (((i)&0xfe0) << 20 | ((i)&0x1f) << 7)
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#define RISCVF_IMMB(i) (((i)&0x1000) << 19 | ((i)&0x800) >> 4 | ((i)&0x7e0) << 20 | ((i)&0x1e) << 7)
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#define RISCVF_IMMU(i) (((i)&0xfffff) << 12)
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#define RISCVF_IMMJ(i) (((i)&0x100000) << 11 | ((i)&0xff000) | ((i)&0x800) << 9 | ((i)&0x7fe) << 20)
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/* Encode helpers. */
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#define RISCVF_W_HI(w) ((w) - ((((w)&0xfff)^0x800) - 0x800))
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#define RISCVF_W_LO(w) ((w)&0xfff)
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#define RISCVF_HI(i) ((RISCVF_W_HI(i) >> 12) & 0xfffff)
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#define RISCVF_LO(i) RISCVF_W_LO(i)
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/* Check for valid field range. */
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#define RISCVF_SIMM_OK(x, b) ((((x) + (1 << (b-1))) >> (b)) == 0)
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#define RISCVF_UIMM_OK(x, b) (((x) >> (b)) == 0)
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#define checku11(i) RISCVF_UIMM_OK(i, 11)
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#define checki12(i) RISCVF_SIMM_OK(i, 12)
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#define checki13(i) RISCVF_SIMM_OK(i, 13)
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#define checki20(i) RISCVF_SIMM_OK(i, 20)
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#define checki21(i) RISCVF_SIMM_OK(i, 21)
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#define checki32auipc(i) (checki32(i) && (int32_t)(i) < 0x7ffff800)
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typedef enum RISCVIns {
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/* --- RVI --- */
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RISCVI_LUI = 0x00000037,
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RISCVI_AUIPC = 0x00000017,
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RISCVI_JAL = 0x0000006f,
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RISCVI_JALR = 0x00000067,
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RISCVI_ADDI = 0x00000013,
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RISCVI_SLTI = 0x00002013,
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RISCVI_SLTIU = 0x00003013,
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RISCVI_XORI = 0x00004013,
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RISCVI_ORI = 0x00006013,
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RISCVI_ANDI = 0x00007013,
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RISCVI_SLLI = 0x00001013,
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RISCVI_SRLI = 0x00005013,
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RISCVI_SRAI = 0x40005013,
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RISCVI_ADD = 0x00000033,
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RISCVI_SUB = 0x40000033,
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RISCVI_SLL = 0x00001033,
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RISCVI_SLT = 0x00002033,
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RISCVI_SLTU = 0x00003033,
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RISCVI_XOR = 0x00004033,
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RISCVI_SRL = 0x00005033,
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RISCVI_SRA = 0x40005033,
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RISCVI_OR = 0x00006033,
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RISCVI_AND = 0x00007033,
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RISCVI_LB = 0x00000003,
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RISCVI_LH = 0x00001003,
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RISCVI_LW = 0x00002003,
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RISCVI_LBU = 0x00004003,
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RISCVI_LHU = 0x00005003,
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RISCVI_SB = 0x00000023,
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RISCVI_SH = 0x00001023,
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RISCVI_SW = 0x00002023,
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RISCVI_BEQ = 0x00000063,
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RISCVI_BNE = 0x00001063,
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RISCVI_BLT = 0x00004063,
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RISCVI_BGE = 0x00005063,
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RISCVI_BLTU = 0x00006063,
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RISCVI_BGEU = 0x00007063,
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RISCVI_ECALL = 0x00000073,
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RISCVI_EBREAK = 0x00100073,
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RISCVI_NOP = 0x00000013,
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RISCVI_MV = 0x00000013,
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RISCVI_NOT = 0xfff04013,
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RISCVI_NEG = 0x40000033,
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RISCVI_RET = 0x00008067,
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RISCVI_ZEXT_B = 0x0ff07013,
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#if LJ_TARGET_RISCV64
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RISCVI_LWU = 0x00007003,
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RISCVI_LD = 0x00003003,
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RISCVI_SD = 0x00003023,
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RISCVI_ADDIW = 0x0000001b,
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RISCVI_SLLIW = 0x0000101b,
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RISCVI_SRLIW = 0x0000501b,
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RISCVI_SRAIW = 0x4000501b,
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RISCVI_ADDW = 0x0000003b,
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RISCVI_SUBW = 0x4000003b,
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RISCVI_SLLW = 0x0000103b,
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RISCVI_SRLW = 0x0000503b,
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RISCVI_SRAW = 0x4000503b,
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RISCVI_NEGW = 0x4000003b,
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RISCVI_SEXT_W = 0x0000001b,
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#endif
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/* --- RVM --- */
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RISCVI_MUL = 0x02000033,
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RISCVI_MULH = 0x02001033,
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RISCVI_MULHSU = 0x02002033,
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RISCVI_MULHU = 0x02003033,
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RISCVI_DIV = 0x02004033,
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RISCVI_DIVU = 0x02005033,
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RISCVI_REM = 0x02006033,
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RISCVI_REMU = 0x02007033,
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#if LJ_TARGET_RISCV64
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RISCVI_MULW = 0x0200003b,
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RISCVI_DIVW = 0x0200403b,
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RISCVI_DIVUW = 0x0200503b,
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RISCVI_REMW = 0x0200603b,
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RISCVI_REMUW = 0x0200703b,
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#endif
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/* --- RVF --- */
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RISCVI_FLW = 0x00002007,
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RISCVI_FSW = 0x00002027,
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RISCVI_FMADD_S = 0x00000043,
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RISCVI_FMSUB_S = 0x00000047,
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RISCVI_FNMSUB_S = 0x0000004b,
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RISCVI_FNMADD_S = 0x0000004f,
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RISCVI_FADD_S = 0x00000053,
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RISCVI_FSUB_S = 0x08000053,
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RISCVI_FMUL_S = 0x10000053,
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RISCVI_FDIV_S = 0x18000053,
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RISCVI_FSQRT_S = 0x58000053,
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RISCVI_FSGNJ_S = 0x20000053,
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RISCVI_FSGNJN_S = 0x20001053,
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RISCVI_FSGNJX_S = 0x20002053,
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RISCVI_FMIN_S = 0x28000053,
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RISCVI_FMAX_S = 0x28001053,
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RISCVI_FCVT_W_S = 0xc0000053,
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RISCVI_FCVT_WU_S = 0xc0100053,
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RISCVI_FMV_X_W = 0xe0000053,
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RISCVI_FEQ_S = 0xa0002053,
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RISCVI_FLT_S = 0xa0001053,
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RISCVI_FLE_S = 0xa0000053,
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RISCVI_FCLASS_S = 0xe0001053,
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RISCVI_FCVT_S_W = 0xd0000053,
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RISCVI_FCVT_S_WU = 0xd0100053,
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RISCVI_FMV_W_X = 0xf0000053,
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RISCVI_FMV_S = 0x20000053,
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RISCVI_FNEG_S = 0x20001053,
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RISCVI_FABS_S = 0x20002053,
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#if LJ_TARGET_RISCV64
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RISCVI_FCVT_L_S = 0xc0200053,
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RISCVI_FCVT_LU_S = 0xc0300053,
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RISCVI_FCVT_S_L = 0xd0200053,
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RISCVI_FCVT_S_LU = 0xd0300053,
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#endif
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/* --- RVD --- */
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RISCVI_FLD = 0x00003007,
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RISCVI_FSD = 0x00003027,
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RISCVI_FMADD_D = 0x02000043,
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RISCVI_FMSUB_D = 0x02000047,
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RISCVI_FNMSUB_D = 0x0200004b,
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RISCVI_FNMADD_D = 0x0200004f,
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RISCVI_FADD_D = 0x02000053,
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RISCVI_FSUB_D = 0x0a000053,
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RISCVI_FMUL_D = 0x12000053,
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RISCVI_FDIV_D = 0x1a000053,
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RISCVI_FSQRT_D = 0x5a000053,
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RISCVI_FSGNJ_D = 0x22000053,
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RISCVI_FSGNJN_D = 0x22001053,
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RISCVI_FSGNJX_D = 0x22002053,
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RISCVI_FMIN_D = 0x2a000053,
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RISCVI_FMAX_D = 0x2a001053,
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RISCVI_FCVT_S_D = 0x40100053,
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RISCVI_FCVT_D_S = 0x42000053,
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RISCVI_FEQ_D = 0xa2002053,
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RISCVI_FLT_D = 0xa2001053,
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RISCVI_FLE_D = 0xa2000053,
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RISCVI_FCLASS_D = 0xe2001053,
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RISCVI_FCVT_W_D = 0xc2000053,
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RISCVI_FCVT_WU_D = 0xc2100053,
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RISCVI_FCVT_D_W = 0xd2000053,
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RISCVI_FCVT_D_WU = 0xd2100053,
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RISCVI_FMV_D = 0x22000053,
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RISCVI_FNEG_D = 0x22001053,
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RISCVI_FABS_D = 0x22002053,
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#if LJ_TARGET_RISCV64
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RISCVI_FCVT_L_D = 0xc2200053,
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RISCVI_FCVT_LU_D = 0xc2300053,
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RISCVI_FMV_X_D = 0xe2000053,
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RISCVI_FCVT_D_L = 0xd2200053,
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RISCVI_FCVT_D_LU = 0xd2300053,
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RISCVI_FMV_D_X = 0xf2000053,
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#endif
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/* --- Zifencei --- */
|
||||
RISCVI_FENCE = 0x0000000f,
|
||||
RISCVI_FENCE_I = 0x0000100f,
|
||||
|
||||
/* --- Zicsr --- */
|
||||
RISCVI_CSRRW = 0x00001073,
|
||||
RISCVI_CSRRS = 0x00002073,
|
||||
RISCVI_CSRRC = 0x00003073,
|
||||
RISCVI_CSRRWI = 0x00005073,
|
||||
RISCVI_CSRRSI = 0x00006073,
|
||||
RISCVI_CSRRCI = 0x00007073,
|
||||
|
||||
/* --- RVB --- */
|
||||
/* Zba */
|
||||
RISCVI_SH1ADD = 0x20002033,
|
||||
RISCVI_SH2ADD = 0x20004033,
|
||||
RISCVI_SH3ADD = 0x20006033,
|
||||
#if LJ_TARGET_RISCV64
|
||||
RISCVI_ADD_UW = 0x0800003b,
|
||||
|
||||
RISCVI_SH1ADD_UW = 0x2000203b,
|
||||
RISCVI_SH2ADD_UW = 0x2000403b,
|
||||
RISCVI_SH3ADD_UW = 0x2000603b,
|
||||
|
||||
RISCVI_SLLI_UW = 0x0800101b,
|
||||
|
||||
RISCVI_ZEXT_W = 0x0800003b,
|
||||
#endif
|
||||
/* Zbb */
|
||||
RISCVI_ANDN = 0x40007033,
|
||||
RISCVI_ORN = 0x40006033,
|
||||
RISCVI_XNOR = 0x40004033,
|
||||
|
||||
RISCVI_CLZ = 0x60001013,
|
||||
RISCVI_CTZ = 0x60101013,
|
||||
|
||||
RISCVI_CPOP = 0x60201013,
|
||||
|
||||
RISCVI_MAX = 0x0a006033,
|
||||
RISCVI_MAXU = 0x0a007033,
|
||||
RISCVI_MIN = 0x0a004033,
|
||||
RISCVI_MINU = 0x0a005033,
|
||||
|
||||
RISCVI_SEXT_B = 0x60401013,
|
||||
RISCVI_SEXT_H = 0x60501013,
|
||||
#if LJ_TARGET_RISCV64
|
||||
RISCVI_ZEXT_H = 0x0800403b,
|
||||
#endif
|
||||
|
||||
RISCVI_ROL = 0x60001033,
|
||||
RISCVI_ROR = 0x60005033,
|
||||
RISCVI_RORI = 0x60005013,
|
||||
|
||||
RISCVI_ORC_B = 0x28705013,
|
||||
|
||||
#if LJ_TARGET_RISCV64
|
||||
RISCVI_REV8 = 0x6b805013,
|
||||
|
||||
RISCVI_CLZW = 0x6000101b,
|
||||
RISCVI_CTZW = 0x6010101b,
|
||||
|
||||
RISCVI_CPOPW = 0x6020101b,
|
||||
|
||||
RISCVI_ROLW = 0x6000103b,
|
||||
RISCVI_RORIW = 0x6000501b,
|
||||
RISCVI_RORW = 0x6000503b,
|
||||
#endif
|
||||
/* NYI: Zbc, Zbs */
|
||||
|
||||
/* --- Zicond --- */
|
||||
RISCVI_CZERO_EQZ = 0x0e005033,
|
||||
RISCVI_CZERO_NEZ = 0x0e007033,
|
||||
|
||||
/* --- Zfa --- */
|
||||
RISCVI_FLI_S = 0xf0100053,
|
||||
RISCVI_FMINM_S = 0x28002053,
|
||||
RISCVI_FMAXM_S = 0x28003053,
|
||||
RISCVI_FROUND_S = 0x40400053,
|
||||
RISCVI_FROUNDNX_S = 0x40500053,
|
||||
RISCVI_FCVTMOD_W_D = 0xc2801053,
|
||||
RISCVI_FLEQ_S = 0xa0004053,
|
||||
RISCVI_FLTQ_S = 0xa0005053,
|
||||
RISCVI_FLI_D = 0xf2100053,
|
||||
RISCVI_FMINM_D = 0x2a002053,
|
||||
RISCVI_FMAXM_D = 0x2a003053,
|
||||
RISCVI_FROUND_D = 0x42400053,
|
||||
RISCVI_FROUNDNX_D = 0x42500053,
|
||||
RISCVI_FLEQ_D = 0xa2004053,
|
||||
RISCVI_FLTQ_D = 0xa2005053,
|
||||
|
||||
RISCVI_FROUND_S_RTZ = 0x40401053,
|
||||
RISCVI_FROUND_S_RDN = 0x40402053,
|
||||
RISCVI_FROUND_S_RUP = 0x40403053,
|
||||
RISCVI_FROUNDNX_S_RTZ = 0x40501053,
|
||||
RISCVI_FROUNDNX_S_RDN = 0x40502053,
|
||||
RISCVI_FROUNDNX_S_RUP = 0x40503053,
|
||||
RISCVI_FROUND_D_RTZ = 0x42401053,
|
||||
RISCVI_FROUND_D_RDN = 0x42402053,
|
||||
RISCVI_FROUND_D_RUP = 0x42403053,
|
||||
RISCVI_FROUNDNX_D_RTZ = 0x42501053,
|
||||
RISCVI_FROUNDNX_D_RDN = 0x42502053,
|
||||
RISCVI_FROUNDNX_D_RUP = 0x42503053,
|
||||
|
||||
/* TBD: RVV?, RVP?, RVJ? */
|
||||
|
||||
/* --- XThead* --- */
|
||||
/* XTHeadBa */
|
||||
RISCVI_TH_ADDSL = 0x0000100b,
|
||||
|
||||
/* XTHeadBb */
|
||||
RISCVI_TH_SRRI = 0x1000100b,
|
||||
#if LJ_TARGET_RISCV64
|
||||
RISCVI_TH_SRRIW = 0x1400100b,
|
||||
#endif
|
||||
RISCVI_TH_EXT = 0x0000200b,
|
||||
RISCVI_TH_EXTU = 0x0000300b,
|
||||
RISCVI_TH_FF0 = 0x8400100b,
|
||||
RISCVI_TH_FF1 = 0x8600100b,
|
||||
RISCVI_TH_REV = 0x8200100b,
|
||||
#if LJ_TARGET_RISCV64
|
||||
RISCVI_TH_REVW = 0x9000100b,
|
||||
#endif
|
||||
RISCVI_TH_TSTNBZ = 0x8000100b,
|
||||
|
||||
/* XTHeadBs */
|
||||
RISCVI_TH_TST = 0x8800100b,
|
||||
|
||||
/* XTHeadCondMov */
|
||||
RISCVI_TH_MVEQZ = 0x4000100b,
|
||||
RISCVI_TH_MVNEZ = 0x4200100b,
|
||||
|
||||
/* XTHeadMac */
|
||||
RISCVI_TH_MULA = 0x2000100b,
|
||||
RISCVI_TH_MULAH = 0x2800100b,
|
||||
#if LJ_TARGET_RISCV64
|
||||
RISCVI_TH_MULAW = 0x2400100b,
|
||||
#endif
|
||||
RISCVI_TH_MULS = 0x2200100b,
|
||||
RISCVI_TH_MULSH = 0x2a00100b,
|
||||
RISCVI_TH_MULSW = 0x2600100b,
|
||||
|
||||
/* NYI: XTHeadMemIdx, XTHeadFMemIdx, XTHeadMemPair */
|
||||
} RISCVIns;
|
||||
|
||||
typedef enum RISCVRM {
|
||||
RISCVRM_RNE = 0,
|
||||
RISCVRM_RTZ = 1,
|
||||
RISCVRM_RDN = 2,
|
||||
RISCVRM_RUP = 3,
|
||||
RISCVRM_RMM = 4,
|
||||
RISCVRM_DYN = 7,
|
||||
} RISCVRM;
|
||||
|
||||
static const uint16_t riscv_fli_map_hi16[32] = {
|
||||
0xbff0u, // -1
|
||||
0x0010u, // min
|
||||
0x3ef0u, // 2^-16
|
||||
0x3f00u, // 2^-15
|
||||
0x3f70u, // 2^-8
|
||||
0x3f80u, // 2^-7
|
||||
0x3fb0u, // 2^-4
|
||||
0x3fc0u, // 2^-3, 0.125
|
||||
0x3fd0u, // 2^-2, 0.25
|
||||
0x3fd4u, // 0.3125
|
||||
0x3fd8u, // 0.375
|
||||
0x3fdcu, // 0.4375
|
||||
0x3fe0u, // 0.5
|
||||
0x3fe4u, // 0.625
|
||||
0x3fe8u, // 0.75
|
||||
0x3fecu, // 0.875
|
||||
0x3ff0u, // 1
|
||||
0x3ff4u, // 1.25
|
||||
0x3ff8u, // 1.5
|
||||
0x3ffcu, // 1.75
|
||||
0x4000u, // 2
|
||||
0x4004u, // 2.5
|
||||
0x4008u, // 3
|
||||
0x4010u, // 4
|
||||
0x4020u, // 8
|
||||
0x4030u, // 16
|
||||
0x4060u, // 128
|
||||
0x4070u, // 256
|
||||
0x40e0u, // 2^15, 32768
|
||||
0x40f0u, // 2^16, 65536
|
||||
0x7ff0u, // inf
|
||||
0x7ff8u, // canonical nan
|
||||
};
|
||||
|
||||
#endif
|
||||
Loading…
Reference in New Issue
Block a user