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ARM, PPC, MIPS: Improve XLOAD operand fusion and register hinting.

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This commit is contained in:
Mike Pall 2012-08-27 20:25:54 +02:00
parent 1e477e6487
commit 30f458fb4d
4 changed files with 9 additions and 5 deletions
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6
src/lj_asm.c
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@ -1749,8 +1749,12 @@ static void asm_setup_regsp(ASMState *as)
}
break;
#endif
/* Do not propagate hints across type conversions. */
/* Do not propagate hints across type conversions or loads. */
case IR_TOBIT:
case IR_XLOAD:
#if !LJ_TARGET_ARM
case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
#endif
break;
case IR_CONV:
if (irt_isfp(ir->t) || (ir->op2 & IRCONV_SRCMASK) == IRT_NUM ||

2
src/lj_asm_arm.h
View File

@ -237,7 +237,7 @@ static void asm_fusexref(ASMState *as, ARMIns ai, Reg rd, IRRef ref,
{
IRIns *ir = IR(ref);
Reg base;
if (ra_noreg(ir->r) && mayfuse(as, ref)) {
if (ra_noreg(ir->r) && canfuse(as, ir)) {
int32_t lim = (!LJ_SOFTFP && (ai & 0x08000000)) ? 1024 :
(ai & 0x04000000) ? 4096 : 256;
if (ir->o == IR_ADD) {

2
src/lj_asm_mips.h
View File

@ -187,7 +187,7 @@ static void asm_fusexref(ASMState *as, MIPSIns mi, Reg rt, IRRef ref,
{
IRIns *ir = IR(ref);
Reg base;
if (ra_noreg(ir->r) && mayfuse(as, ref)) {
if (ra_noreg(ir->r) && canfuse(as, ir)) {
if (ir->o == IR_ADD) {
int32_t ofs2;
if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {

4
src/lj_asm_ppc.h
View File

@ -166,7 +166,7 @@ static void asm_fusexref(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
{
IRIns *ir = IR(ref);
Reg base;
if (ra_noreg(ir->r) && mayfuse(as, ref)) {
if (ra_noreg(ir->r) && canfuse(as, ir)) {
if (ir->o == IR_ADD) {
int32_t ofs2;
if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {
@ -214,7 +214,7 @@ static void asm_fusexrefx(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
{
IRIns *ira = IR(ref);
Reg right, left;
if (mayfuse(as, ref) && ira->o == IR_ADD && ra_noreg(ira->r)) {
if (canfuse(as, ira) && ira->o == IR_ADD && ra_noreg(ira->r)) {
left = ra_alloc2(as, ira, allow);
right = (left >> 8); left &= 255;
} else {