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ARM, PPC, MIPS: Improve XLOAD operand fusion and register hinting.
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parent
1e477e6487
commit
30f458fb4d
@ -1749,8 +1749,12 @@ static void asm_setup_regsp(ASMState *as)
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}
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}
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break;
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break;
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#endif
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#endif
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/* Do not propagate hints across type conversions. */
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/* Do not propagate hints across type conversions or loads. */
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case IR_TOBIT:
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case IR_TOBIT:
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case IR_XLOAD:
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#if !LJ_TARGET_ARM
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case IR_ALOAD: case IR_HLOAD: case IR_ULOAD: case IR_VLOAD:
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#endif
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break;
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break;
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case IR_CONV:
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case IR_CONV:
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if (irt_isfp(ir->t) || (ir->op2 & IRCONV_SRCMASK) == IRT_NUM ||
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if (irt_isfp(ir->t) || (ir->op2 & IRCONV_SRCMASK) == IRT_NUM ||
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@ -237,7 +237,7 @@ static void asm_fusexref(ASMState *as, ARMIns ai, Reg rd, IRRef ref,
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{
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{
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IRIns *ir = IR(ref);
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IRIns *ir = IR(ref);
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Reg base;
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Reg base;
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if (ra_noreg(ir->r) && mayfuse(as, ref)) {
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if (ra_noreg(ir->r) && canfuse(as, ir)) {
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int32_t lim = (!LJ_SOFTFP && (ai & 0x08000000)) ? 1024 :
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int32_t lim = (!LJ_SOFTFP && (ai & 0x08000000)) ? 1024 :
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(ai & 0x04000000) ? 4096 : 256;
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(ai & 0x04000000) ? 4096 : 256;
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if (ir->o == IR_ADD) {
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if (ir->o == IR_ADD) {
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@ -187,7 +187,7 @@ static void asm_fusexref(ASMState *as, MIPSIns mi, Reg rt, IRRef ref,
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{
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{
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IRIns *ir = IR(ref);
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IRIns *ir = IR(ref);
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Reg base;
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Reg base;
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if (ra_noreg(ir->r) && mayfuse(as, ref)) {
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if (ra_noreg(ir->r) && canfuse(as, ir)) {
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if (ir->o == IR_ADD) {
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if (ir->o == IR_ADD) {
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int32_t ofs2;
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int32_t ofs2;
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if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {
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if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {
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@ -166,7 +166,7 @@ static void asm_fusexref(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
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{
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{
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IRIns *ir = IR(ref);
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IRIns *ir = IR(ref);
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Reg base;
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Reg base;
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if (ra_noreg(ir->r) && mayfuse(as, ref)) {
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if (ra_noreg(ir->r) && canfuse(as, ir)) {
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if (ir->o == IR_ADD) {
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if (ir->o == IR_ADD) {
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int32_t ofs2;
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int32_t ofs2;
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if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {
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if (irref_isk(ir->op2) && (ofs2 = ofs + IR(ir->op2)->i, checki16(ofs2))) {
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@ -214,7 +214,7 @@ static void asm_fusexrefx(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
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{
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{
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IRIns *ira = IR(ref);
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IRIns *ira = IR(ref);
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Reg right, left;
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Reg right, left;
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if (mayfuse(as, ref) && ira->o == IR_ADD && ra_noreg(ira->r)) {
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if (canfuse(as, ira) && ira->o == IR_ADD && ra_noreg(ira->r)) {
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left = ra_alloc2(as, ira, allow);
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left = ra_alloc2(as, ira, allow);
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right = (left >> 8); left &= 255;
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right = (left >> 8); left &= 255;
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} else {
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} else {
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