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ARM64: Fix stores to vmstate.

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Contributed by Stefan Pejic.
This commit is contained in:
Mike Pall 2017-04-17 12:00:04 +02:00
parent cced1786b9
commit 18efb331a4
1 changed files with 6 additions and 6 deletions
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12
src/vm_arm64.dasc
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@ -1947,7 +1947,7 @@ static void build_subroutines(BuildCtx *ctx)
| stp d30, d31, [sp, #30*8] | stp d30, d31, [sp, #30*8]
| ldr CARG1, [sp, #64*8] // Load original value of lr. | ldr CARG1, [sp, #64*8] // Load original value of lr.
| add CARG3, sp, #64*8 // Recompute original value of sp. | add CARG3, sp, #64*8 // Recompute original value of sp.
| mv_vmstate CARG4, EXIT | mv_vmstate CARG4w, EXIT
| stp xzr, CARG3, [sp, #62*8] // Store 0/sp in RID_LR/RID_SP. | stp xzr, CARG3, [sp, #62*8] // Store 0/sp in RID_LR/RID_SP.
| sub CARG1, CARG1, lr | sub CARG1, CARG1, lr
| ldr L, GL->cur_L | ldr L, GL->cur_L
@ -1955,7 +1955,7 @@ static void build_subroutines(BuildCtx *ctx)
| ldr BASE, GL->jit_base | ldr BASE, GL->jit_base
| sub CARG1, CARG1, #2 | sub CARG1, CARG1, #2
| ldr CARG2w, [lr] // Load trace number. | ldr CARG2w, [lr] // Load trace number.
| st_vmstate CARG4 | st_vmstate CARG4w
|.if ENDIAN_BE |.if ENDIAN_BE
| rev32 CARG2, CARG2 | rev32 CARG2, CARG2
|.endif |.endif
@ -1994,12 +1994,12 @@ static void build_subroutines(BuildCtx *ctx)
| str BASE, L->base | str BASE, L->base
| ldr CARG2, LFUNC:CARG2->pc | ldr CARG2, LFUNC:CARG2->pc
| str xzr, GL->jit_base | str xzr, GL->jit_base
| mv_vmstate CARG4, INTERP | mv_vmstate CARG4w, INTERP
| ldr KBASE, [CARG2, #PC2PROTO(k)] | ldr KBASE, [CARG2, #PC2PROTO(k)]
| // Modified copy of ins_next which handles function header dispatch, too. | // Modified copy of ins_next which handles function header dispatch, too.
| ldrb RBw, [PC, # OFS_OP] | ldrb RBw, [PC, # OFS_OP]
| ldr INSw, [PC], #4 | ldr INSw, [PC], #4
| st_vmstate CARG4 | st_vmstate CARG4w
| cmp RBw, #BC_FUNCC+2 // Fast function? | cmp RBw, #BC_FUNCC+2 // Fast function?
| add TMP1, GL, INS, uxtb #3 | add TMP1, GL, INS, uxtb #3
| bhs >4 | bhs >4
@ -3702,9 +3702,9 @@ static void build_ins(BuildCtx *ctx, BCOp op, int defop)
|.if JIT |.if JIT
| // RA = base (ignored), RC = traceno | // RA = base (ignored), RC = traceno
| ldr CARG1, [GL, #GL_J(trace)] | ldr CARG1, [GL, #GL_J(trace)]
| mov CARG2, #0 // Traces on ARM64 don't store the trace #, so use 0. | mov CARG2w, #0 // Traces on ARM64 don't store the trace #, so use 0.
| ldr TRACE:RC, [CARG1, RC, lsl #3] | ldr TRACE:RC, [CARG1, RC, lsl #3]
| st_vmstate CARG2 | st_vmstate CARG2w
| ldr RA, TRACE:RC->mcode | ldr RA, TRACE:RC->mcode
| str BASE, GL->jit_base | str BASE, GL->jit_base
| str L, GL->tmpbuf.L | str L, GL->tmpbuf.L