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PPC: Fuse BSWAP with XLOAD/XSTORE to lwbrx/stwbrx.
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ca2b923026
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@ -205,6 +205,22 @@ static void asm_fusexref(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
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emit_fai(as, pi, rt, base, ofs);
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emit_fai(as, pi, rt, base, ofs);
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}
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}
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/* Fuse XLOAD/XSTORE reference into indexed-only load/store operand. */
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static void asm_fusexrefx(ASMState *as, PPCIns pi, Reg rt, IRRef ref,
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RegSet allow)
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{
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IRIns *ira = IR(ref);
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Reg right, left;
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if (mayfuse(as, ref) && ira->o == IR_ADD && ra_noreg(ira->r)) {
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left = ra_alloc2(as, ira, allow);
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right = (left >> 8); left &= 255;
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} else {
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right = ra_alloc1(as, ref, allow);
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left = RID_R0;
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}
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emit_tab(as, pi, rt, left, right);
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}
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/* Fuse to multiply-add/sub instruction. */
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/* Fuse to multiply-add/sub instruction. */
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static int asm_fusemadd(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pir)
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static int asm_fusemadd(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pir)
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{
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{
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@ -886,10 +902,17 @@ static void asm_xload(ASMState *as, IRIns *ir)
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static void asm_xstore(ASMState *as, IRIns *ir)
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static void asm_xstore(ASMState *as, IRIns *ir)
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{
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{
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// NYI: fuse with bswap to stwbrx.
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IRIns *irb;
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Reg src = ra_alloc1(as, ir->op2, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR);
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if (mayfuse(as, ir->op2) && (irb = IR(ir->op2))->o == IR_BSWAP &&
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asm_fusexref(as, asm_fxstoreins(ir), src, ir->op1,
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ra_noreg(irb->r) && (irt_isint(ir->t) || irt_isu32(ir->t))) {
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rset_exclude(RSET_GPR, src));
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/* Fuse BSWAP with XSTORE to stwbrx. */
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Reg src = ra_alloc1(as, irb->op1, RSET_GPR);
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asm_fusexrefx(as, PPCI_STWBRX, src, ir->op1, rset_exclude(RSET_GPR, src));
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} else {
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Reg src = ra_alloc1(as, ir->op2, irt_isfp(ir->t) ? RSET_FPR : RSET_GPR);
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asm_fusexref(as, asm_fxstoreins(ir), src, ir->op1,
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rset_exclude(RSET_GPR, src));
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}
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}
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}
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static void asm_ahuvload(ASMState *as, IRIns *ir)
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static void asm_ahuvload(ASMState *as, IRIns *ir)
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@ -1410,17 +1433,23 @@ nofuse:
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static void asm_bitswap(ASMState *as, IRIns *ir)
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static void asm_bitswap(ASMState *as, IRIns *ir)
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{
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{
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// NYI: fuse with XLOAD to lwbrx.
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Reg dest = ra_dest(as, ir, RSET_GPR);
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Reg dest = ra_dest(as, ir, RSET_GPR);
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Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
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IRIns *irx;
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Reg tmp = dest;
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if (mayfuse(as, ir->op1) && (irx = IR(ir->op1))->o == IR_XLOAD &&
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if (tmp == left) {
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ra_noreg(irx->r) && (irt_isint(irx->t) || irt_isu32(irx->t))) {
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tmp = RID_TMP;
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/* Fuse BSWAP with XLOAD to lwbrx. */
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emit_mr(as, dest, RID_TMP);
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asm_fusexrefx(as, PPCI_LWBRX, dest, irx->op1, RSET_GPR);
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} else {
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Reg left = ra_alloc1(as, ir->op1, RSET_GPR);
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Reg tmp = dest;
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if (tmp == left) {
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tmp = RID_TMP;
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emit_mr(as, dest, RID_TMP);
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}
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emit_rot(as, PPCI_RLWIMI, tmp, left, 24, 16, 23);
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emit_rot(as, PPCI_RLWIMI, tmp, left, 24, 0, 7);
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emit_rotlwi(as, tmp, left, 8);
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}
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}
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emit_rot(as, PPCI_RLWIMI, tmp, left, 24, 16, 23);
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emit_rot(as, PPCI_RLWIMI, tmp, left, 24, 0, 7);
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emit_rotlwi(as, tmp, left, 8);
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}
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}
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static void asm_bitop(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pik)
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static void asm_bitop(ASMState *as, IRIns *ir, PPCIns pi, PPCIns pik)
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@ -240,6 +240,9 @@ typedef enum PPCIns {
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PPCI_LHAX = 0x7c0002ae,
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PPCI_LHAX = 0x7c0002ae,
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PPCI_STHX = 0x7c00032e,
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PPCI_STHX = 0x7c00032e,
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PPCI_LWBRX = 0x7c00042c,
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PPCI_STWBRX = 0x7c00052c,
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PPCI_LFSX = 0x7c00042e,
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PPCI_LFSX = 0x7c00042e,
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PPCI_LFDX = 0x7c0004ae,
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PPCI_LFDX = 0x7c0004ae,
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PPCI_STFSX = 0x7c00052e,
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PPCI_STFSX = 0x7c00052e,
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